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US 12,769,443 B2Granted
Completion flag for memory operations
AssigneeMicron Technology, Inc.
InventorsGiuseppe Cariello, Jonathan S. Parry
Life of this patent
Estimating the term…
Abstract
Methods, systems, and devices for using a completion flag for memory operations are described. A completion flag for a memory device may indicate whether at least one access operation has been completed at the memory device. A controller may poll the completion flag, and if the completion flag indicates that at least one access operation has been completed at the memory device, the controller may poll a status register for the memory device to obtain additional information regarding one or more completed access operations at the memory device.
Claims19
An apparatus, comprising:
- processing circuitry coupled with a plurality of memory dies via a bus, the processing circuitry external to the plurality of memory dies and configured to cause the apparatus to:
- transmit, via the bus that is coupled with each memory die of the plurality of memory dies, a single polling request for a plurality of flags comprising a respective flag corresponding to each memory die of the plurality of memory dies;
- receive, via respective input/output lines of a plurality of input/output lines of the bus and in response to the single polling request, respective indications of a respective state of each flag of the plurality of flags, the respective indications comprising a first indication received via a first input/output line of the plurality of input/output lines of the bus and a second indication received via a second input/output line of the plurality of input/output lines of the bus;
- transmit, to a first memory die of the plurality of memory dies based at least in part on the respective indications of the respective state of each of the plurality of flags, a command to output data, wherein the command to output the data is based at least in part on a first flag corresponding to the first memory die of the plurality of memory dies indicating a completion of at least one access operation at the first memory die;
- and
- receive, from the first memory die based at least in part on the command to output the data, the data corresponding to the at least one access operation at the first memory die.
3 more elements
A memory system, comprising:
- one or more memory dies each comprising a plurality of planes;
- one or more registers associated with the one or more memory dies, each register of the one or more registers configured to store a plurality of status bits each corresponding to a respective one of the plurality of planes;
- and
- processing circuitry coupled with the one or more memory dies and configured to cause the memory system to:
- set a first status bit of a register of the one or more registers corresponding to a first plane of the plurality of planes included in a first memory die of the one or more memory dies based at least in part on a completion of an access operation at the first plane;
- set a first flag stored at the first memory die to indicate a completion of at least one access operation at the first memory die based at least in part on the completion of the access operation at the first plane;
- receive, after setting the first flag to indicate the completion of the at least one access operation at the first memory die, a single polling request for the first flag and for at least a second flag stored at a second memory die;
- output, in response to the single polling request for the first flag and for at least the second flag, a first indication via a first input/output line of a plurality of input/output lines of a bus that the first flag is set and at least a second indication via a second input/output line of the plurality of input/output lines of the bus of whether the second flag is set;
- receive, based at least in part on the first flag to indicate the completion of the at least one access operation at the first memory die being set, a command to output data associated with the first plane;
- and
- output, based at least in part on the command, data corresponding to the access operation at the first plane.
8 more elements
A non-transitory computer-readable medium storing code comprising instructions which, when executed by processing circuitry of a memory device, cause the memory device to:
- set a first status bit of a register based at least in part on a completion of an access operation at a first plane of a plurality of planes of a first memory die of the memory device, wherein the register is included in the memory device and is configured to store a plurality of status bits each corresponding to a respective one of the plurality of planes, and wherein the first status bit corresponds to the first plane;
- set a first flag stored at the first memory die to indicate a completion of at least one access operation at the first memory die based at least in part on the completion of the access operation at the first plane, wherein the first flag comprises a single bit;
- receive, after setting the first flag to indicate the completion of the at least one access operation, a single polling request for the first flag and for at least a second flag stored at a second memory die;
- output, in response to the single polling request for the first flag and for at least the second flag, a first indication via a first input/output line of a plurality of input/output lines of a bus that the first flag is set and at least a second indication via a second input/output line of the plurality of input/output lines of the bus of whether the second flag is set;
- receive, based at least in part on the first flag to indicate the completion of the at least one access operation at the first memory die being set, a command to output data associated with the first plane;
- and
- output, based at least in part on the command, data corresponding to the access operation at the first plane.
4 more elements
Dependencies are inferred from the claim text.