Thermal measurement for complex thermal stack up products

A method, comprising:

• determining an R deviation percentage threshold for each thermal interface layer in a set of thermal interface layers, wherein the set of thermal interface layers is part of a chip package or a board package undergoing a thermal test;
• calculating an R deviation for each thermal interface layer in the set of thermal interface layers using the R deviation percentage threshold, wherein the R deviation is an integral of the change in power over a time interval;
• obtaining thermal measurements from a testing jig that supplies power to the chip package or the board package and measures thermal characteristics over a time interval;
• determining a measured time parameter from the R deviation and the thermal measurements from the chip package or the board package for each thermal interface layer in the set of thermal interface layers;
• identifying at least one thermal failure parameter for at least one thermal interface layer in the set of thermal interface layers by comparing the measured time parameter to a thermal interface layer gold value for each respective thermal interface layer;
• and
• moving, by a package sorter using the at least one thermal failure parameter, the chip package or the board package to a designated place, wherein the chip package or the board package that passes each thermal interface layer test is placed in a first group, the chip package or the board package that fails at least one thermal interface layer test and is repairable is placed in a second group, and the chip package or the board package that fails at least one thermal interface layer test and is not repairable is placed in a third group.