Method for estimating performance values of chips, computing system, and non-transitory computer-readable storage medium

A non-transitory computer-readable storage medium configured to store one or more computer-readable instructions, when one or more processors executing the one or more computer-readable instructions, the one or more computer-readable instructions cause the one or more processors to conduct following steps to estimate a plurality of performance values of a plurality of chips:

• (A) using a plurality of oscillation period vectors of a to-be-divided chip set to train a first neural network model corresponding to the to-be-divided chip set, to obtain a training error of the to-be-divided chip set, wherein when step (A) is conducted for the first time, the to-be-divided chip set includes the plurality of chips;
• (B) dividing the to-be-divided chip set into a plurality of divided chip sets according to the training error;
• and
• (C) using a plurality of oscillation period vectors of the plurality of divided chip sets as training data of a second neural network model, so that the second neural network model outputs a plurality of weight vectors respectively corresponding to the plurality of divided chip sets,
• wherein a product of one or more oscillation period vectors of each divided chip set and a weight vector of the divided chip set is larger than a product of the one or more oscillation period vectors of the divided chip set and a weight vector of each of rest of divided chip sets.

A computing system, comprising one or more processors, wherein the one or more processors are configured to conduct following steps to estimate a plurality of performance values of a plurality of chips:

• (A) using a plurality of oscillation period vectors of a to-be-divided chip set to train a first neural network model corresponding to the to-be-divided chip set, to obtain a training error of the to-be-divided chip set, wherein when step (A) is conducted for the first time, the to-be-divided chip set includes the plurality of chips;
• (B) dividing the to-be-divided chip set into a plurality of divided chip sets according to the training error;
• and
• (C) using a plurality of oscillation period vectors of the plurality of divided chip sets as training data of a second neural network model, so that the second neural network model outputs a plurality of weight vectors respectively corresponding to the plurality of divided chip sets,
• wherein a product of one or more oscillation period vectors of each divided chip set and a weight vector of the divided chip set is larger than a product of the one or more oscillation period vectors of the divided chip set and a weight vector of each of rest of divided chip sets.