Semiconductor package having partially plated lead flank and method of making the same

A method for fabricating a semiconductor package, the method comprising the steps of:

• providing a lead frame array comprising
• one or more lead frames, each lead frame of the one or more lead frames comprising one or more die paddles;
• a first dam bar comprising:
• a first plurality of dam bar connecting sections;
• a second dam bar comprising:
• a second plurality of dam bar connecting sections;
• a first plurality of slots between the first dam bar and a first side of said each lead frame;
• a second plurality of slots between the second dam bar and a second side of said each lead frame, the second side of said each lead frame being opposite the first side of said each lead frame;
• a first plurality of leads extending away from the one or more die paddles along a first direction, each of the first plurality of leads being connected to the first dam bar;
• and
• a second plurality of leads extending away from the one or more die paddles along a second direction opposite the first direction, each of the second plurality of leads being connected to the second dam bar;
• mounting a chip on the one or more die paddles;
• forming a molding encapsulation enclosing the chip;
• applying a cutting process or a punching process removing the first plurality of dam bar connecting sections and the second plurality of dam bar connecting sections;
• plating tin on portions of the lead frame array not covered by the molding encapsulation;
• and
• applying a singulation process;
• wherein a first plurality of rectangular holes are between the first plurality of dam bar connecting sections and the one or more die paddles, and
• wherein a lateral dimension of each of the first plurality of rectangular holes between the first plurality of dam bar connecting sections and the one or more die paddles is smaller than a lateral dimension of a corresponding dam bar connecting section of the first plurality of dam bar connecting sections.