Semiconductor package and method of manufacturing the semiconductor package

A semiconductor package, comprising:

• a lower redistribution wiring layer including first redistribution wirings;
• a semiconductor chip on the lower redistribution wiring layer, wherein a first surface of the semiconductor chip comprising chip pads faces the lower redistribution wiring layer;
• a sealing member on the semiconductor chip and on the lower redistribution wiring layer, wherein the sealing member exposes a second surface of the semiconductor chip opposite to the first surface;
• a plurality of vertical conductive structures penetrating the sealing member and electrically connected to the first redistribution wirings;
• a marking pattern in a marking layer on the second surface of the semiconductor chip;
• and
• an upper redistribution wiring layer including a layer of second redistribution wirings electrically connected to the plurality of vertical conductive structures, wherein the layer of second redistribution wiring is on the sealing member and the marking layer,
• wherein an upper surface of the marking pattern is coplanar with an upper surface of the sealing member.

A semiconductor package, comprising:

• a lower redistribution wiring layer having a first region and a second region adjacent the first region, the lower redistribution wiring layer including first redistribution wirings;
• a semiconductor chip on the first region of the lower redistribution wiring layer, wherein a first surface of the semiconductor chip comprising chip pads faces the lower redistribution wiring layer;
• a sealing member on the semiconductor chip and on the lower redistribution wiring layer, wherein the sealing member exposes a second surface of the semiconductor chip opposite to the first surface;
• a plurality of vertical conductive structures penetrating the sealing member on the second region of the lower redistribution wiring layer and electrically connected to the first redistribution wirings;
• a marking pattern on the second surface of the semiconductor chip;
• seed layer pads on respective end portions of the vertical conductive structures that are exposed by the sealing member at an upper surface thereof;
• and
• an upper redistribution wiring layer on the sealing member and the marking pattern, the upper redistribution wiring layer including second redistribution wirings on the seed layer pads,
• wherein the sealing member is on a side surface of the marking pattern and is on side surfaces of the seed layer pads.