Method for manufacturing semiconductor device and method for manufacturing power control circuit

A method for manufacturing a semiconductor device, the method comprising:

• a) connecting a back surface of each of a plurality of current-carrying semiconductor elements having each of a plurality of P-N junction diodes built-in to a first principal surface of a conductor plate;
• b) connecting a conductor piece on a front surface of each of the plurality of current-carrying semiconductor elements;
• c) conducting, after step a) and step b) are performed, a current-carrying test of the plurality of P-N junction diodes with a second principal surface of the conductor plate exposed on a bottom surface of an intermediate product of a semiconductor device including the plurality of current-carrying semiconductor elements, the conductor plate, and the conductor piece;
• d) forming each of two or more gate electrodes on a front surface of each of two or more current-carrying semiconductor elements included in the plurality of current-carrying semiconductor elements;
• e) connecting a relay board including a gate circuit pattern having conductivity to the first principal surface;
• f) electrically connecting the two or more gate electrodes to each other via the gate circuit pattern;
• and
• g) electrically reconnecting the two or more gate electrodes to each other via the gate circuit pattern after step c) is performed,
• wherein step c) is performed after step d), step e), step f) are performed.

A method for manufacturing a semiconductor device, the method comprising:

• a) connecting a back surface of each of a plurality of current-carrying semiconductor elements having each of a plurality of P-N junction diodes built-in to a first principal surface of a conductor plate;
• b) connecting a conductor piece on a front surface of each of the plurality of current-carrying semiconductor elements;
• c) conducting, after step a) and step b) are performed, a current-carrying test of the plurality of P-N junction diodes by applying a common potential to each of the plurality of current-carrying semiconductor elements via a second principal surface of the conductor plate with the second principal surface of the conductor plate exposed on a bottom surface of an intermediate product of a semiconductor device including the plurality of current-carrying semiconductor elements, the conductor plate, and the conductor piece;
• h) forming each of two or more source electrodes on a front surface of each of two or more current-carrying semiconductor elements included in the plurality of current-carrying semiconductor elements;
• i) connecting a relay board including a source circuit pattern having conductivity to the first principal surface;
• and
• j) electrically connecting the two or more source electrodes to each other via the source circuit pattern,
• wherein step j) is performed after step c) is performed, and
• during step c), the second principal surface of the conductor plate is electrically connected to the plurality of current-carrying semiconductor elements.

A method for manufacturing a semiconductor device, the method comprising:

• a) connecting a back surface of each of a plurality of current-carrying semiconductor elements having each of a plurality of P-N junction diodes built-in to a first principal surface of a conductor plate;
• b) connecting a conductor piece on a front surface of each of the plurality of current-carrying semiconductor elements;
• c) conducting, after step a) and step b) are performed, a current-carrying test of the plurality of P-N junction diodes by applying a common potential to each of the plurality of current-carrying semiconductor elements via a second principal surface of the conductor plate with the second principal surface of the conductor plate exposed on a bottom surface of an intermediate product of a semiconductor device including the plurality of current-carrying semiconductor elements, the conductor plate, and the conductor piece;
• p) connecting a relay board including a gate circuit pattern having conductivity and a source circuit pattern having conductivity to the first principal surface;
• q) connecting a plurality of spacer conductors to the gate circuit pattern and the source circuit pattern;
• and
• r) forming, after step c) is performed, resin sealing material covering the plurality of current-carrying semiconductor elements, the relay board, at least a portion of the conductor plate, at least a portion of the conductor piece, and at least a portion of the plurality of spacer conductors,
• wherein during step c), the second principal surface of the conductor plate is electrically connected to the plurality of current-carrying semiconductor elements.