Integrated circuit including standard cells and method of designing the same

An integrated circuit comprising:

• a first cell in a first row extending in a first direction;
• a first power line extending in the first direction in a power rail layer, the first power line being configured to provide a first supply voltage to the first cell;
• and
• a first pattern and a second pattern adjacent to each other, each extending in the first direction in a first wiring layer, a first boundary extending in the first direction between the first row and a second row adjacent to the first row being between the first pattern and the second pattern, the first wiring layer being over the power rail layer,
• wherein the first cell includes:
• at least one pattern extending in the first direction in the first wiring layer;
• and
• at least one transistor between the power rail layer and the first wiring layer such that the first wiring layer is at least partially over the at least one transistor and the power rail layer is at least partially under the at least one transistor, and
• wherein the first pattern is configured to receive a first input signal or a first output signal of the first cell.

An integrated circuit comprising:

• a plurality of cells in a plurality of rows extending in a first direction;
• a plurality of power lines extending in the first direction in a power rail layer, the plurality of power lines being configured to provide a first supply voltage or a second supply voltage to each of the plurality of cells;
• and
• a plurality of first patterns overlapping respective boundaries of the plurality of rows or immediately adjacent to the respective boundaries, the plurality of first patterns extending in the first direction in a first wiring layer, the first wiring layer being over the power rail layer,
• wherein each of the plurality of cells includes:
• at least one second pattern extending in the first direction in the first wiring layer;
• and
• at least one transistor between the power rail layer and the first wiring layer such that the first wiring layer is at least partially over the at least one transistor and the power rail layer is at least partially under the at least one transistor, and
• wherein the plurality of first patterns include a first pattern configured to receive a first input signal or a first output signal of a first cell among the plurality of cells in a first row among the plurality of rows.