Synaptic array structure based on CMOS integration technology and method of fabricating the synaptic array structure

A synaptic array structure includes:

• a semiconductor substrate;
• an isolation insulating layer positioned in a predetermined area on the semiconductor substrate to isolate devices;
• CMOS peripheral circuits including PMOSFET and NMOSFET devices provided on the semiconductor substrate;
• and
• a plurality of TFT-type synaptic devices arranged in an array on the isolation insulating layer;
• wherein, the TFT-type synaptic device includes:
• a source and drain positioned on the isolation insulating layer and spaced apart from each other by a predetermined distance, and made of a semiconductor material doped with a first type of impurities;
• a semiconductor body positioned between the source and the drain and made of a semiconductor material doped with a second type of impurities opposite to the first type;
• oxide layers positioned between the semiconductor body and the source and between the semiconductor body and the drain;
• a semiconductor layer for channel positioned on upper surfaces of the semiconductor body and the oxide layers, configured to electrically connect the source and the drain by forming a channel, and made of a semiconductor material;
• a TFT gate insulating layer positioned on an upper surface of the semiconductor layer for channel and comprising of at least one insulating layer;
• and
• a TFT gate electrode positioned on an upper surface of the TFT gate insulating layer and made of a conductive material.