Semiconductor device with source/drain including stressor elements and method for manufacturing the same

A method for manufacturing a semiconductor device, comprising:

• forming two recesses at two opposite sides of a stack, the stack including channel features and sacrificial features which are disposed to alternate with the channel features, the channel features and the sacrificial features being made of different materials, the channel features including first semiconductor elements;
• recessing the sacrificial features to form grooves;
• forming inner spacers respectively in the grooves such that the inner spacers are disposed between corresponding adjacent ones of the channel features;
• and
• growing two source/drain features respectively in the two recesses, each of the two source/drain features having a p-type conductivity and including a major portion, the major portion being formed by growing epitaxial regions on the channel features, growing amorphous regions on the inner spacers, and growing a central region to fill a respective one of the two recesses, the major portion including
• second semiconductor elements,
• p-type dopants,
• stressor elements which are different from the p-type dopants and which have an atomic radius less than an atomic radius of the second semiconductor elements, and
• a certain degree of dislocations which propagate from the amorphous regions into the epitaxial regions or the central region of the major portion such that the major portion including the stressor elements applies a compressive stress to the channel features;
• and
• after growing the two source/drain features, removing the sacrificial features.

A method for manufacturing a semiconductor device, comprising:

• forming a recess in a base portion and at a side of a stack, the stack being disposed on the base portion and including channel features and sacrificial features which are disposed to alternate with the channel features, the channel features and the sacrificial features being made of different materials, the channel features including first semiconductor elements and having a {110} crystal plane facing the recess;
• growing a semiconductor layer on a bottom of the recess by a bottom-up epitaxial growth, where the semiconductor layer has a growth rate over a {100} crystal plane of the base portion higher than a growth rate over the {110} crystal plane of the channel features;
• depositing a dielectric layer on the semiconductor layer;
• and
• growing a source/drain portion on the dielectric layer and in the recess, the source/drain portion having an n-type conductivity and including
• silicon elements,
• n-type dopants,
• stressor elements which are different from the n-type dopants and having an atomic radius greater than an atomic radius of the silicon elements, and
• a certain degree of dislocations present such that the source/drain portion including the stressor elements applies a tensile stress to the channel features.