Fringe-gated castellated FET

A method of forming a field effect transistor, comprising:

• providing a substrate and forming a superlattice of stacked conducting channels on the substrate;
• forming a source and a drain spaced-apart from each other on the superlattice;
• forming alternating castellations and trenches in the superlattice between the source and the drain, the castellations having sidewalls that cut-down through the superlattice to form the trenches and edges of the stacked conducting channels that terminate at the sidewalls;
• forming a fringe field dielectric that fills lower volumes of the trenches, the fringe field dielectric having a top surface within the trenches that is lower than a height of the trenches and higher than first edges of first conducting channels among the stacked conducting channels, such that the fringe field dielectric is adjacent to the first edges;
• and
• forming a gate electrode overlaying the fringe field dielectric and the castellations, the gate electrode having a lower surface within the trenches that is lower than the height of the trenches and higher than the first edges such that the gate electrode is not adjacent to the first edges.