Three-dimensional non-volatile memory device with reduced chip size

A non-volatile memory device comprising:

• a first semiconductor layer comprising a memory cell array that includes a plurality of vertical channel structures;
• and
• a second semiconductor layer stacked on the first semiconductor layer in a vertical direction and comprising a row decoder,
• wherein the first semiconductor layer comprises:
• a plurality of word lines stacked in the vertical direction;
• a layer comprising at least one string select line stacked on the plurality of word lines;
• and
• a plurality of pass transistors,
• wherein each of the plurality of pass transistors comprises a gate and a vertical channel extending in the vertical direction,
• wherein the gate is at a same level as the at least one string select line relative to a substrate,
• wherein the plurality of pass transistors electrically connect the plurality of word lines to the row decoder.

A non-volatile memory device comprising:

• a first semiconductor layer comprising a memory cell array;
• and
• a second semiconductor layer stacked on the first semiconductor layer in a vertical direction and comprising a row decoder,
• wherein the first semiconductor layer comprises:
• a plurality of word lines stacked in the vertical direction;
• a layer comprising at least one string select line between the plurality of word lines and a bonding surface between the first semiconductor layer and the second semiconductor layer;
• and
• a plurality of first pass transistors,
• wherein each of the plurality of first pass transistors comprises a gate and a vertical channel extending in the vertical direction,
• wherein the gate is at a same level as the at least one string select line relative to a substrate,
• wherein the plurality of first pass transistors electrically connect the plurality of word lines to the row decoder.