Three-dimensional ferroelectric memory device

A three-dimensional (3D) ferroelectric memory device comprising:

• a substrate;
• a plurality of insulating layers stacked on an upper surface of the substrate;
• a plurality of gate electrodes between the plurality of insulating layers;
• a plurality of gate insulating layers on corresponding side surfaces of the plurality of gate electrodes;
• a ferroelectric layer on side surfaces of the plurality of insulating layers;
• a plurality of intermediate electrodes between the plurality of gate insulating layers and the ferroelectric layer;
• and
• a channel layer on the ferroelectric layer,
• wherein the plurality of gate insulating layers are between the plurality of gate electrodes and the plurality of intermediate electrodes, and
• wherein the ferroelectric layer is between the plurality of intermediate electrodes and the channel layer.