Three-dimensional semiconductor memory device and electronic system including the same

A three-dimensional semiconductor memory device, comprising:

• a substrate that includes a cell array region and a connection region;
• a stack structure that includes a plurality of dielectric layers and a plurality of gate electrodes that are alternately stacked on the substrate;
• a plurality of vertical channel structures that extend through the stack structure on the cell array region;
• a plurality of gate contacts that extend through the stack structure on the connection region, the plurality of gate contacts being connected to the plurality of gate electrodes, respectively;
• a plurality of dummy vertical structures that extend through the stack structure on the connection region;
• a plurality of dielectric patterns in contact with a plurality of sidewalls of the plurality of gate contacts;
• a plurality of bit lines on the stack structure and connected to the plurality of vertical channel structures;
• and
• a plurality of conductive lines on the stack structure and connected to the plurality of gate contacts,
• wherein each gate contact of the plurality of gate contacts includes:
• a first portion;
• and
• a plurality of second portions that protrude from the first portion,
• wherein two or three second portions of the plurality of second portions extend in a first direction, and
• wherein remaining second portions of the plurality of second portions extend in a second direction that intersects the first direction.

An electronic system comprising:

• a three-dimensional semiconductor memory device including:
• a substrate that includes a cell array region and a connection region,
• a stack structure that includes a plurality of gate electrodes stacked on the substrate,
• a plurality of dummy vertical structures that extend through the stack structure on the connection region,
• a gate contact that is adjacent to the plurality of dummy vertical structures and that extends through a portion of the stack structure,
• an input/output pad electrically connected to a plurality of peripheral circuits;
• and
• a controller that has electrical connection through the input/output pad with the three-dimensional semiconductor memory device and that is configured to control the three-dimensional semiconductor memory device, and
• a dielectric pattern that surrounds a lateral surface of the gate contact,
• wherein the gate contact is spaced apart from the plurality of dummy vertical structures,
• wherein the stack structure extends in one direction while surrounding the plurality of dummy vertical structures and the gate contact, and
• wherein the gate contact includes:
• a first portion;
• and
• a plurality of second portions, wherein each second portion of the plurality of second portions protrudes from the first portion and extends between two adjacent dummy vertical structures of the plurality of dummy vertical structures.