Layout structure of memory cell array for non-volatile memory
AssigneeeMemory Technology Inc.
InventorsChih-Hsin Chen, Shih-Chen Wang, Bo-Chang Li
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Abstract
A layout structure of a memory cell array for a non-volatile memory is provided. The memory cell array includes plural memory cells. Each memory cell includes a capacitor, an erase gate element, a select transistor, a floating gate transistor and a switch transistor. Moreover, plural wells are formed in a semiconductor substrate, and a floating gate is formed over the semiconductor substrate. The locations of the well regions and the shape of the floating gate are specially designed. Moreover, the plural memory cells with at least two shapes are constructed on the semiconductor substrate. Consequently, the layout area of the layout structure of the memory cell array can be effectively reduced.
Claims20
A layout structure of a memory cell array for a non-volatile memory, the layout structure comprising:
- a first first-type well region, a second first-type well region, a first second-type well region and a second second-type well region, wherein the second first-type well region is arranged between the first second-type well region and the second second-type well region, and the first second-type well region is arranged between the first first-type well region and the second first-type well region;
- a first gate, a second gate and a first floating gate formed on a surface of the second second-type well region, wherein the first floating gate is extended from the second second-type well region to the first first-type well region through the second first-type well region and the first second-type well region;
- a first first-type doped region, a second first-type doped region, a third first-type doped region and a fourth first-type doped region formed in the surface of the second second-type well region, wherein the first gate spans a surface between the first first-type doped region and the second first-type doped region, the first floating gate spans a surface between the second first-type doped region and the third first-type doped region, and the second gate spans a surface between the third first-type doped region and the fourth first-type doped region;
- a first second-type doped region formed in the first first-type well region, wherein the first second-type doped region is located beside the first floating gate;
- a first contact terminal formed on the first second-type doped region and connected with an erase line;
- and
- a second contact terminal formed on the second first-type well region and connected with a coupling line.
A layout structure of a memory cell array for a non-volatile memory, the layout structure comprising:
- a first first-type well region, a second first-type well region, a first second-type well region, a second second-type well region and a third second-type well region, wherein the second first-type well region is arranged between the first second-type well region and the second second-type well region, the first second-type well region is arranged between the first first-type well region and the second first-type well region, and the first first-type well region is arranged between the first second-type well region and the third second-type well region;
- a first gate, a second gate and a first floating gate formed on a surface of the third second-type well region, wherein the first floating gate is extended from the third second-type well region to the second first-type well region through the first first-type well region and the first second-type well region;
- a first first-type doped region, a second first-type doped region, a third first-type doped region and a fourth first-type doped region formed in a surface of the third second-type well region, wherein the first gate spans a surface between the first first-type doped region and the second first-type doped region, a first floating gate spans a surface between the second first-type doped region and the third first-type doped region, and the second gate spans a surface between the third first-type doped region and the fourth first-type doped region;
- a first second-type doped region formed in the first first-type well region, wherein the first second-type doped region is located beside the first floating gate;
- a first contact terminal formed on the first second-type doped region and connected with an erase line;
- and
- a second contact terminal formed on the second first-type well region and connected with a coupling line.
Dependencies are inferred from the claim text.