Semiconductor device including a multiple-time programmable memory cell

A semiconductor device, comprising:

• a memory structure;
• a first metallization layer coupled with the memory structure;
• a second metallization layer, above the first metallization layer, comprising:
• a first metal line, configured as a write bit line metallization layer of the memory structure, coupled with the first metallization layer through one or more first interconnect structures;
• and
• a connection pad structure, spaced apart from the first metal line, coupled with the first metallization layer through one or more second interconnect structures;
• and
• a third metallization layer, above the second metallization layer, comprising:
• a second metal line configured as a read bit line metallization layer of the memory structure,
• wherein the second metal line is coupled with the first metallization layer through the connection pad structure.

A method, comprising:

• forming a doped region in a substrate of a semiconductor device;
• forming, above the doped region, a first gate structure of a first transistor structure of a memory structure;
• forming, above the doped region, a second gate structure of a second transistor structure of the memory structure;
• forming, in the doped region, a first source/drain region adjacent to the first gate structure;
• forming, in the doped region, a second source/drain region adjacent to the second gate structure;
• forming a first metallization layer above the first source/drain region and the second source/drain region;
• forming, above the first source/drain region, a write bit line metallization layer coupled with the first metallization layer;
• and
• forming, above the second source/drain region and above the write bit line metallization layer, a read bit line metallization layer coupled with the first metallization layer.