Semiconductor device and method of manufacturing the same

A semiconductor device comprising:

• a plurality of bit lines each extending in a first direction on a substrate and spaced apart from each other in a second direction perpendicular to the first direction;
• a plurality of semiconductor patterns disposed on each of the plurality of bit lines and arranged in a hexagonal array, the plurality of semiconductor patterns comprising:
• a plurality of first semiconductor patterns disposed on a first bit line from among the plurality of bit lines and located at a first distance from a first sidewall of the first bit line, and a plurality of second semiconductor patterns located at a second distance that is greater than the first distance from the first sidewall on the first bit line;
• a plurality of word lines each extending in the second direction and surrounding a sidewall of each of the plurality of semiconductor patterns;
• a plurality of storage nodes respectively disposed on the plurality of semiconductor patterns;
• a plurality of gate insulating layer structures located between the plurality of word lines and the plurality of semiconductor patterns;
• and
• an insulating liner disposed on an upper side of the sidewall of each of the plurality of semiconductor patterns, the insulating liner comprising an air space therein,
• wherein each of the plurality of word lines comprises a main gate portion surrounding at least one semiconductor pattern among the plurality of semiconductor patterns, and a connection gate portion disposed between two main gate portions adjacent to each other in the second direction, the connection gate portion being connected to the two main gate portions, and
• wherein each of the plurality of gate insulating layer structures comprises:
• a first dielectric layer surrounding the sidewall of each of the plurality of semiconductor patterns and having an upper surface at a higher level than an upper surface of each of the plurality of semiconductor patterns;
• and
• a second dielectric layer surrounding the sidewall of each of the plurality of semiconductor patterns on the first dielectric layer, and having an upper surface at a lower level than the upper surface of each of the plurality of semiconductor patterns.

A semiconductor device comprising:

• a plurality of bit lines each extending in a first direction on a substrate and spaced apart from each other in a second direction perpendicular to the first direction;
• a plurality of semiconductor patterns disposed on each of the plurality of bit lines and arranged in a hexagonal array, the plurality of semiconductor patterns comprising a plurality of first semiconductor patterns disposed on a first bit line from among the plurality of bit lines and located at a first distance from a first sidewall of the first bit line, and a plurality of second semiconductor patterns located at a second distance that is greater than the first distance from the first sidewall on the first bit line;
• a plurality of word lines each extending in the second direction and surrounding a sidewall of each of the plurality of semiconductor patterns;
• a plurality of gate insulating layer structures located between the plurality of word lines and the plurality of semiconductor patterns;
• an insulating liner disposed on an upper side of the sidewall of each of the plurality of semiconductor patterns, the insulating liner comprising an air space therein;
• and
• a plurality of storage nodes respectively disposed on the plurality of semiconductor patterns, the plurality of storage nodes comprising a lower electrode, a capacitor dielectric layer, and an upper electrode,
• wherein a sidewall of a bottom portion of the lower electrode is covered by the insulating liner.