Semiconductor device

A semiconductor device, comprising:

• a first structure disposed on a memory cell array region of a substrate, the first structure including a cell gate structure and a cell device isolation region defining a cell active region;
• a second structure disposed on a peripheral circuit region of the substrate, the second structure including a peripheral device isolation region defining a peripheral active region;
• a bit line structure and a bit line capping pattern that are stacked on the first structure;
• a peripheral gate structure on the second structure;
• gate spacers on side surfaces of the peripheral gate structure;
• a peripheral interlayer insulating layer disposed on the second structure and covering the peripheral gate structure and the gate spacers;
• a peripheral contact plug penetrating through the peripheral interlayer insulating layer and electrically connected to a peripheral source/drain region in the peripheral active region;
• and
• a peripheral interconnection line electrically connected to the peripheral contact plug and in contact with an upper surface of the peripheral interlayer insulating layer,
• wherein the peripheral gate structure includes a peripheral gate dielectric layer, a peripheral gate electrode, and a peripheral gate capping pattern that are stacked,
• wherein a bottom end of the peripheral interlayer insulating layer is disposed at a level lower than a level of a bottom surface of the peripheral gate electrode,
• wherein the bit line capping pattern includes a lower bit line capping layer and an upper bit line capping layer that are stacked, and
• wherein a material of the upper bit line capping layer is same as a material of the peripheral interlayer insulating layer.

A semiconductor device, comprising:

• a first structure disposed on a memory cell array region of a substrate, the first structure including a cell gate structure and a cell device isolation region defining a cell active region;
• a second structure disposed on a peripheral circuit region of the substrate, the second structure including a peripheral device isolation region defining a peripheral active region;
• a bit line structure and a bit line capping pattern that are stacked on the first structure;
• peripheral gate structures intersecting the peripheral active region and separate from each other on the second structure;
• gate spacers on side surfaces of the peripheral gate structures;
• a peripheral interlayer insulating layer disposed on the second structure and covering the peripheral gate structures and the gate spacers;
• a peripheral contact plug penetrating through the peripheral interlayer insulating layer, electrically connected to a peripheral source/drain region in the peripheral active region, disposed between the peripheral gate structures and in contact with the gate spacers;
• and
• a peripheral interconnection line electrically connected to the peripheral contact plug and in contact with a top surface of the peripheral interlayer insulating layer,
• wherein each of the peripheral gate structure includes a peripheral gate dielectric layer, a peripheral gate electrode, and a peripheral gate capping pattern that are stacked,
• wherein a bottom end of the peripheral interlayer insulating layer is disposed at a level lower than a level of a bottom surface of the peripheral gate electrode,
• wherein the bit line capping pattern includes a lower bit line capping layer and an upper bit line capping layer that are stacked, and
• wherein a material of the upper bit line capping layer is same as a material of the peripheral interlayer insulating layer.