Memory device and manufacturing method thereof

A manufacturing method of a memory device comprising:

• forming a stack including a first insulating layer, and a first sacrificial layer and a second insulating layer which are sequentially stacked on the first insulating layer;
• forming a patterned stack having at least one pattern portion having a first sacrificial layer pattern obtained from the first sacrificial layer by patterning the stack, wherein the pattern portion has a shape extending in a first direction, and empty spaces are provided on both sides of the pattern portion along a second direction perpendicular to the first direction;
• forming a structure including the patterned stack and an insulating material by filling the empty spaces on both sides of the at least one pattern portion with the insulating material;
• forming a first vertical hole penetrating through the first sacrificial layer pattern of the pattern portion in the structure;
• forming a horizontal hole extending in the first direction by removing the first sacrificial layer pattern exposed by the first vertical hole;
• forming a gate insulating material layer on inner surfaces of the first vertical hole and the horizontal hole, and forming a dummy channel material layer to fill the first vertical hole and the horizontal hole on the gate insulating material layer;
• forming a second vertical hole in a region corresponding to the first vertical hole in the structure where the gate insulating material layer and the dummy channel material layer are formed;
• exposing the gate insulating material layer by removing the first and second insulating layers and the insulating material from a transistor formation region around the second vertical hole of the structure;
• forming a word line surrounding the exposed portion of the gate insulating material layer in the transistor formation region;
• forming a first trench in a capacitor formation region adjacent to the transistor formation region of the structure;
• forming a first recess exposing the gate insulating material layer by removing the first and second insulating layers and the insulating material exposed by the first trench in the capacitor formation region;
• forming a mold insulating layer filling the first recess;
• forming a second recess by removing the dummy channel material layer and the gate insulating material layer from the capacitor formation region, forming an electrode member on an inner surface of the second recess, forming a capacitor including the electrode member, a dielectric layer, and a plate electrode by sequentially forming the dielectric layer and the plate electrode on the electrode member;
• forming an empty channel space by removing the dummy channel material layer from the transistor formation region, and forming a channel material layer connected to the capacitor in the empty channel space to define a transistor including the channel material layer;
• and
• forming a bit line connected to the channel material layer.