Hybrid gate dielectric access device for vertical three-dimensional memory

A memory device, comprising:

• a horizontally oriented access device having a first source/drain region and a second source/drain region separated by a channel region, the access device being operatively controlled by a gate opposing the channel region;
• a multi-layer gate dielectric having a first dielectric material and a second dielectric material separating the gate from the channel region, the second dielectric material being different from the first dielectric material, wherein:
• the multi-layer gate dielectric comprises:
• a first layer having a surface formed in contact with the channel region;
• a second layer having a surface formed in contact with a surface of the first layer opposite the first layer surface formed in contact with the channel region;
• and
• a third layer having a surface formed in contact with a surface of the second layer opposite the second layer surface formed in contact with the surface of the first layer;
• the gate is formed in contact with a surface of the third layer opposite the third layer surface formed in contact with the surface of the second layer;
• and
• the second layer has a vertical thickness (t2) which is less than a vertical thickness (t1) of the first layer and is less than a vertical thickness (t3) of the third layer;
• a horizontally oriented storage node coupled to the second source/drain region of the access device;
• and
• a vertically oriented digit line coupled to the first source/drain region of the access device.

A method of forming vertical three-dimensional (3D) memory, comprising:

• forming a first horizontally oriented thin film transistor (TFT) in a first horizontal tier of a multi-tier 3D memory, the first TFT having a first source/drain region and a second source/drain region separated by a channel region;
• forming a multi-layer gate dielectric, having a first dielectric material as a first layer and a second dielectric material as a second layer, separating a gate from the channel region to form an access device, the second dielectric material being different from the first dielectric material, wherein the first dielectric material is formed to have a first vertical thickness (t1), and wherein the second dielectric material is formed to have a second vertical thickness (t2) which is less than the first vertical thickness (t1);
• forming a horizontally oriented storage node coupled to the second source/drain region of the access device;
• and
• forming a vertically oriented digit line coupled to the first source/drain region of the access device.