Memory with three-dimensional vertical structure and method of manufacturing memory with three-dimensional vertical structure

A memory with a three-dimensional vertical structure, comprising:

• a semiconductor substrate, a first isolation layer, a first transistor and a second transistor stacked in sequence from bottom to top;
• wherein the first transistor comprises a first source layer, a second isolation layer, a first drain layer and a third isolation layer stacked in sequence from bottom to top and a first through hole, wherein the first through hole penetrates the third isolation layer, the first drain layer and the second isolation layer in sequence and stops at the first source layer, and a first active layer, a first gate dielectric layer and a first gate layer are stacked in sequence on an inner sidewall of the first through hole;
• wherein the second transistor comprises a fourth isolation layer, a second source layer and a fifth isolation layer stacked in sequence from bottom to top and a second through hole, wherein the second through hole penetrates the fifth isolation layer, the second source layer and the fourth isolation layer in sequence and stops at the first gate layer, and a second active layer, a second gate dielectric layer and a second gate layer are stacked in sequence on an inner sidewall of the second through hole;
• and
• wherein a projection of the second through hole on the first isolation layer is surrounded by a projection of the first through hole on the first isolation layer.