Memory device, method of manufacturing memory device, and electronic apparatus including memory device

A memory device, comprising:

• a first connection line layer, a second connection line layer, a third connection line layer, and a fourth connection line layer that are sequentially disposed in a vertical direction with respect to a substrate, wherein the first connection line layer comprises a plurality of first conductive lines extending parallel to each other in a first direction, one of the second connection line layer and the third connection line layer comprises a plurality of conductive lines extending parallel to each other in a second direction intersecting the first direction, and the fourth connection line layer comprises a plurality of fourth conductive lines extending parallel to each other in a third direction;
• a plurality of memory cells, wherein each memory cell extends vertically from a corresponding first conductive line in the first connection line layer and respectively forms electrical connections with the second connection line layer or a corresponding conductive line in the second connection line layer, the third connection line layer or a corresponding conductive line in the third connection line layer, and a corresponding fourth conductive line in the fourth connection line layer, and each memory cell comprises a first transistor, a second transistor, and a third transistor that are stacked on each other in the vertical direction,
• wherein the first transistor comprises:
• a first active layer, comprising a first source/drain region electrically connected with the second connection line layer or the corresponding conductive line in the second connection line layer, a second source/drain region, and a channel region between the first source/drain region of the first transistor and the second source/drain region of the first transistor in the vertical direction;
• a first gate dielectric layer on the first active layer;
• and
• a first gate conductor layer on the first gate dielectric layer, wherein the first gate conductor layer extends towards the corresponding first conductive line in the first connection line layer to be electrically connected to the corresponding first conductive line in the first connection line layer,
• wherein the second transistor comprises:
• a second active layer, comprising a first source/drain region, a second source/drain region electrically connected with the third connection line layer or the corresponding conductive line in the third connection line layer, and a channel region between the first source/drain region of the second transistor and the second source/drain region of the second transistor in the vertical direction, wherein the second source/drain region of the first transistor and the first source/drain region of the second transistor are close to each other and electrically connected with each other;
• a second gate dielectric layer on the second active layer;
• and
• a second gate conductor layer on the second gate dielectric layer, wherein the second gate conductor layer and the first gate conductor layer are electrically isolated from each other, and
• wherein the third transistor comprises:
• a third active layer, comprising a first source/drain region electrically connected with the second gate conductor layer, a second source/drain region electrically connected with the corresponding fourth conductive line in the fourth connection line layer, and a channel region between the first source/drain region of the third transistor and the second source/drain region of the third transistor in the vertical direction;
• a third gate dielectric layer on the third active layer;
• and
• a third gate conductor layer on the third gate dielectric layer, and
• a fifth connection line layer above the memory cell, wherein the fifth connection line layer comprises a plurality of fifth conductive lines extending in a fourth direction intersecting the third direction, and the third gate conductor layer of each memory cell is electrically connected to a corresponding fifth conductive line in the fifth connection line layer,
• wherein the first active layer, the second active layer, and the third active layer are self-aligned in the vertical direction.