Capacitorless dynamic random access memory and methods of formation

A dynamic random access memory (DRAM) cell structure, comprising:

• a first transistor coupled with a word line conductive structure and a bit line conductive structure;
• a second transistor above the first transistor and coupled with the first transistor and to a ground conductive structure,
• wherein the second transistor comprises:
• a first plurality of source/drain regions;
• a first channel layer above the first plurality of source/drain regions,
• wherein the first channel layer comprises:
• a first elongated portion;
• a second elongated portion;
• a third elongated portion coupled with the first elongated portion and the second elongated portion at opposing ends of the third elongated portion;
• a first extension portion;
• and
• a second extension portion that is approximately parallel with the first extension portion,
• wherein the first extension portion and the second extension portion are approximately parallel with the third elongated portion and approximately perpendicular with the first elongated portion and the second elongated portion;
• and
• a first gate structure above the first plurality of source/drain regions and at least partially wrapping around the first channel layer;
• and
• a third transistor above the second transistor and coupled with the second transistor, a write word line conductive structure, and a write bit line conductive structure,
• wherein the third transistor comprises:
• a second plurality of source/drain regions;
• a second channel layer above the second plurality of source/drain regions;
• and
• a second gate structure above the second plurality of source/drain regions and at least partially wrapping around the second channel layer.

A method of forming a transistor of a memory cell, comprising:

• forming, in a dielectric layer, a first source/drain region and a second source/drain region of the transistor;
• forming a dielectric support structure above the first source/drain region and above the second source/drain region;
• forming a channel layer of the transistor such that the channel layer is on the dielectric support structure and above the first source/drain region and the second source/drain region,
• wherein the channel layer wraps around three sides of the dielectric support structure and extends over top surfaces of the first source/drain region and the second source/drain region;
• forming a gate dielectric layer of the transistor over the channel layer;
• forming a spacer layer on the gate dielectric layer prior to forming a gate structure of the transistor;
• and
• forming the gate structure of the transistor on the spacer layer and over the gate dielectric layer.