Circuit board and chip package comprising same
AssigneeLG Innotek Co., Ltd.
InventorsIn Jae Lee, Min Sung Jo
Life of this patent
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Abstract
A circuit board according to an embodiment includes: an insulating layer; and a circuit pattern layer disposed on the insulating layer and formed of an alloy, wherein the alloy includes: a first metal having a content in a range of 60 wt % to 80 wt %; a second metal having a content in a range of 10 wt % to 22 wt %; and a third metal having a content in a range of 3 wt % to 20 wt %; wherein the first metal includes any one of nickel (Ni) and iron (Fe), wherein the second metal includes chromium (Cr), and wherein the third metal includes a metal different from the first metal among nickel (Ni) and iron (Fe).
Claims18
A circuit board for a smart IC card comprising:
- an insulating layer including at least one through hole passing through upper and lower surfaces;
- and
- a circuit pattern layer disposed on the insulating layer and formed of an alloy,
- wherein an upper surface of the circuit pattern layer is a contact portion, and a lower surface of the circuit pattern layer in a region vertically overlapping the through hole is a bonding portion,
- wherein the alloy includes:
- a first metal having a content in a range of 60 wt % to 80 wt %;
- a second metal having a content in a range of 10 wt % to 22 wt %;
- and
- a third metal having a content in a range of 3 wt % to 20 wt %;
- wherein the first metal includes any one of nickel (Ni) and iron (Fe),
- wherein the second metal includes chromium (Cr), and
- wherein the third metal includes a metal different from the first metal among nickel (Ni) and iron (Fe).
A chip package comprising:
- a circuit board for a smart IC card;
- an IC chip disposed on the circuit board;
- and
- a connecting member connecting the circuit board and the IC chip,
- wherein the circuit board includes:
- an insulating layer including at least one through hole passing through upper and lower surfaces;
- a circuit pattern layer disposed on the insulating layer to vertically overlap the through hole and formed of an alloy,
- wherein an upper surface of the circuit pattern layer is a contact portion, and a lower surface of the circuit pattern layer in a region vertically overlapping the through hole is a bonding portion,
- wherein the circuit board includes a surface treatment layer disposed on the bonding portion of the circuit pattern layer,
- wherein the IC chip is attached to a lower surface of the insulating layer,
- wherein the connecting member connects the surface treatment layer and a terminal of the IC chip,
- wherein the alloy includes:
- a first metal having a content in a range of 60 wt % to 80 wt %;
- a second metal having a content in a range of 10 wt % to 22 wt %;
- and
- a third metal having a content in a range of 3 wt % to 20 wt %;
- wherein the first metal includes any one of nickel (Ni) and iron (Fe),
- wherein the second metal includes chromium (Cr), and
- wherein the third metal includes a metal different from the first metal among nickel (Ni) and iron (Fe).
Dependencies are inferred from the claim text.