Performing scrambling and/or descrambling on parallel computing architectures
AssigneeNVIDIA Corporation
InventorAndrea Miele
Life of this patent
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Abstract
Apparatuses, systems, and techniques to descramble or scramble data use a graphics processing unit (GPU) to perform descrambling. For example, in at least one embodiment, generation of a descrambling sequence is distributed among GPU threads for parallel calculation of the descrambling sequence and/or descrambling is distributed among GPU threads for descrambling.
Claims25
A method, comprising:
- generating a descrambling sequence derived from one or more many-to-one Linear Feedback Shift Registers (LFSRs) based, at least in part, on two or more threads of one or more parallel processing units (PPUs) operating on two or more one-to-many LFSRs that are advanced through a number of cycles that differ across the two or more threads with outputs of the two or more one-to-many LFSRs provided as inputs to the one or more many-to-one LFSRs.
A processor, comprising:
- one or more circuits to generate a descrambling sequence derived from one or more many-to-one Linear Feedback Shift Registers (LFSRs) based, at least in part, on two or more threads of one or more parallel processing units (PPUs) operating on two or more one-to-many LFSRs that are advanced through a number of cycles that differ across the two or more threads with outputs of the two or more one-to-many LFSRs provided as inputs to the one or more many-to-one LFSRs.
A computer readable medium having stored thereon a set of instructions, which if performed by one or more processors, cause the one or more processors to generate a descrambling sequence derived from one or more many-to-one Linear Feedback Shift Registers (LFSRs) based, at least in part, on two or more threads of one or more parallel processing units (PPUs) operating on two or more one-to-many LFSRs that are advanced through a number of cycles that differ across the two or more threads with outputs of the two or more one-to-many LFSRs provided as inputs to the one or more many-to-one LFSRs.
A system, comprising:
- one or more processors to generate a descrambling sequence derived from one or more many-to-one Linear Feedback Shift Registers (LFSRs) based, at least in part, on two or more threads of one or more parallel processing units (PPUs) operating on two or more one-to-many LFSRs that are advanced through a number of cycles that differ across the two or more threads with outputs of the two or more one-to-many LFSRs provided as inputs to the one or more many-to-one LFSRs.
Dependencies are inferred from the claim text.