Analog-to-digital converter circuit, digital filter circuit, and control method thereof

An analog-to-digital converter (ADC) circuit, comprising:

• a receiver circuit receiving a first analog input and a second analog input and using the first analog input or the second analog input as an output signal according to a control signal;
• and
• a delta-sigma ADC converting the output signal to generate output data and comprising:
• a differential amplifier amplifying a difference between the output signal and a reference signal to generate an amplified signal;
• an integrator accumulating the amplified signal to generate an integrated signal;
• a quantizer quantizing the integrated signal to generate input data;
• a digital-to-analog converter (DAC) circuit converting the input data to generate the reference signal;
• and
• a digital filter circuit over-sampling the input data according to the control signal to generate the output data,
• wherein:
• in response to the control signal matching a predetermined state:
• the receiver circuit uses the first analog input as the output signal;
• the digital filter circuit over-samples the input data to generate a plurality of first sampled results and stores the first sampled results in a first register circuit;
• and
• the digital filter circuit generates the output data according to the first sampled results,
• in response to the control signal not matching the predetermined state:
• the receiver circuit uses the second analog input as the output signal;
• the digital filter circuit over-samples the input data to generate a plurality of second sampled results and stores the second sampled results in a second register circuit;
• and
• the digital filter circuit generates the output data according to the second sampled results,
• the digital filter circuit comprises:
• an integrator circuit comprising:
• a first integrator comprising:
• a first adder adding the input data and a first register value to generate a first calculation value;
• a first selector circuit selecting the first calculation value as a first output value or a second output value according to the control signal;
• a first register storing the first output value;
• a second register storing the second output value;
• a second selector circuit selecting the first output value stored in the first register or the second output value stored in the second register as the first register value according to the control signal;
• a second integrator connected to the first integrator in series and comprising:
• a second adder adding the first calculation value and a second register value to generate a second calculation value;
• a third selector circuit selecting the second calculation value as a third output value or a fourth output value according to the control signal;
• a third register storing the third output value;
• a fourth register storing the fourth output value;
• a fourth selector circuit selecting the third output value stored in the third register or the fourth output value stored in the fourth register as the second register value according to the control signal;
• a frequency reduction circuit down-sampling the second calculation value to generate a processed value;
• a comb filter circuit comprising:
• a first comb filter comprising:
• a first subtractor subtracting a third register value from the processed value to generate a third calculation value;
• a fifth selector circuit selecting the processed value as a fifth output value or a sixth output value according to the control signal;
• a fifth register storing the fifth output value;
• a sixth register storing the sixth output value;
• a sixth selector circuit selecting the fifth output value stored in the fifth register or the sixth output value stored in the sixth register as the third register value according to the control signal;
• a second comb filter comprising:
• a second subtractor subtracting a fourth register value from the third calculation value to generate a fourth calculation value;
• a seventh selector circuit selecting the third calculation value as a seventh output value or an eighth output value according to the control signal;
• a seventh register storing the seventh output value;
• an eighth register storing the eighth output value;
• an eighth selector circuit selecting the seventh output value stored in the seventh register or the eighth output value stored in the eighth register as the fourth register value according to the control signal.

A digital filter circuit over-sampling input data to generate output data and comprising:

• an integrator circuit comprising:
• a first integrator comprising:
• a first adder adding the input data and a first register value to generate a first calculation value;
• a first selector circuit selecting the first calculation value as a first output value or a second output value according to a control signal;
• a first register storing the first output value;
• a second register storing the second output value;
• a second selector circuit selecting the first output value stored in the first register or the second output value stored in the second register as the first register value according to the control signal;
• a second integrator connected to the first integrator in series and comprising:
• a second adder adding the first calculation value and a second register value to generate a second calculation value;
• a third selector circuit selecting the second calculation value as a third output value or a fourth output value according to the control signal;
• a third register storing the third output value;
• a fourth register storing the fourth output value;
• a fourth selector circuit selecting the third output value stored in the third register or the fourth output value stored in the fourth register as the second register value according to the control signal;
• a frequency reduction circuit down-sampling the second calculation value to generate a processed value;
• a comb filter circuit comprising:
• a first comb filter comprising:
• a first subtractor subtracting a third register value from the processed value to generate a third calculation value;
• a fifth selector circuit selecting the processed value as a fifth output value or a sixth output value according to the control signal;
• a fifth register storing the fifth output value;
• a sixth register storing the sixth output value;
• a sixth selector circuit selecting the fifth output value stored in the fifth register or the sixth output value stored in the sixth register as the third register value according to the control signal;
• a second comb filter comprising:
• a second subtractor subtracting a fourth register value from the third calculation value to generate a fourth calculation value;
• a seventh selector circuit selecting the third calculation value as a seventh output value or an eighth output value according to the control signal;
• a seventh register storing the seventh output value;
• an eighth register storing the eighth output value;
• an eighth selector circuit selecting the seventh output value stored in the seventh register or the eighth output value stored in the eighth register as the fourth register value according to the control signal.