Device and method for multi-chip clock synchronization

A multi-chip clock synchronization method comprising:

• generating a reference clock having a first frequency which is N times lower than a second frequency of a target clock;
• supplying the reference clock having the first frequency to each of multiple chips;
• generating the target clock having the second frequency by multiplying the first frequency of the reference clock in each of the multiple chips by N times when the reference clock of the first frequency is input to each chip;
• and
• synchronizing clocks of the multiple chips based on a target clock having the second frequency;
• wherein the first frequency is determined as a lowest frequency of the reference clock if a jitter is generated when the first frequency of the reference clock is multiplied by N times, and
• wherein the first frequency of the reference clock is determined to be low when a total number of the plurality of chips increases, thereby reducing power consumption due to clock transmission.

A display device comprising:

• a touch panel in which a plurality of touch sensors is disposed;
• a touch driving device configured to drive the plurality of touch sensors;
• and
• a multi-chip clock synchronization device configured to apply a target clock to a plurality of chips of the touch driving device to synchronize clocks of the plurality of chips, wherein
• the multi-chip clock synchronization device includes:
• a reference clock supply unit connected to a plurality of chips and supplying a reference clock of a first frequency to each chip of the plurality of chips;
• and
• a target clock generation unit configured to generate a target clock of a second frequency based on the reference clock of the first frequency input to each chip, wherein
• the reference clock supply unit is configured to generate the reference clock of the first frequency which is N times lower than the second frequency of the target clock to supply the generated reference clock to each chip,
• the target clock generation unit is configured to multiply the first frequency of the reference clock by N times when the reference clock of the first frequency is input to generate the target clock of the second frequency,
• the reference clock supply unit is configured to determine the first frequency as a lowest frequency of the reference clock if a jitter is generated when the target clock generation unit multiplies the first frequency of the reference clock by N times, and
• the reference clock supply unit is further configured to determine the first frequency of the reference clock to be low when a total number of the plurality of chips increases, thereby reducing power consumption due to clock transmission.