Semiconductor package calibrating skew of clock signal, semiconductor device, and operating method of the semiconductor device

An operating method of a semiconductor device, the operating method comprising:

• generating first and second internal clock signal pairs of different phases, based on a clock signal pair received through a complementary clock lane;
• sampling data signals and a track signal received through data lanes in response to rising edges of the first and second internal clock signal pairs;
• detecting a skew status between the track signal and the first and second internal clock signal pairs, based on a number of times a specific logic level of the track signal is sampled in synchronization with each of the first and second internal clock signal pairs;
• and
• shifting phases of the first and second internal clock signal pairs, based on the skew status.

A semiconductor package comprising:

• a first die configured to generate a data signal, to generate a track signal, and to generate a clock signal pair;
• a die-to-die (D2D) interface comprising a first data lane transmitting the data signal, a second data lane transmitting the track signal, and a complementary clock lane transmitting the clock signal pair;
• and
• a second die configured to:
• generate first and second internal clock signal pairs of different phases, based on the clock signal pair,
• sample the data signal and the track signal, based on the first and second internal clock signal pairs,
• detect a skew status between the track signal and the first and second internal clock signal pairs, based on a number of times a specific logic level of the track signal is sampled in synchronization with each of the first and second internal clock signal pairs, and
• adjust phases of the first and second internal clock signal pairs, based on the skew status.