Level shifting circuit with integrated latch

A level shifting circuit with an integrated latch, the level shifting circuit comprising:

• a front stage, wherein an input terminal of the front stage is arranged to receive an input signal, a first clock terminal of the front stage is arranged to receive a first clock, a second clock terminal of the front stage is arranged to receive a second clock, wherein the first clock and the second clock are complementary to each other, the first clock is at a first level during a first phase, and the first clock is at a second level during a second phase;
• a rear stage, wherein an input terminal of the rear stage is connected to an output terminal of the front stage, a first clock terminal of the rear stage is arranged to receive the first clock, a second clock terminal of the rear stage is arranged to receive the second clock, and an output terminal of the rear stage is arranged to generate an output signal,
• wherein during the first phase, the front stage is in a conversion mode, the rear stage is in a propagation mode, and the front stage serves as a level shifter, wherein the input signal in a range between a first supply voltage and a ground voltage is converted into a shifted signal in a range between a second supply voltage and the ground voltage by the front stage, and the rear stage is configured to receive the shifted signal and generate the output signal, wherein the first supply voltage is lower than the second supply voltage,
• wherein during the second phase, the front stage is in a tri-state output mode, the rear stage is in a retention mode, and the rear stage serves as a latch, wherein the output terminal of the front stage has a high output impedance, and the output signal from the rear stage is maintained at a specified logic level and kept unchanged.