Aging resilient level shifter

A level shifter comprising:

• a cross-coupled pair of transistors coupled between a first power supply node and a first pair of nodes, the cross-coupled pair of transistors having a first doping type;
• a pair of isolation transistors coupled between the first pair of nodes and a second pair of nodes, the pair of isolation transistors having a second doping type, the second doping type being complementary to the first doping type, wherein the pair of isolation transistors is selectively disabled by an isolation control signal;
• a pair of cascode transistors coupled between the second pair of nodes and a third pair of nodes, the pair of cascode transistors having the second doping type and being configured to receive a predetermined bias voltage;
• and
• a pair of transistors coupled between the third pair of nodes and a second power supply node, the pair of transistors having the second doping type, the pair of transistors being configured to receive an input signal and a complementary input signal,
• wherein the first power supply node is configured to receive an output power supply voltage level above an output ground and a third power supply node is configured to receive an input power supply voltage level above an input ground, the output power supply voltage level being greater than the input power supply voltage level, the second power supply node being coupled to the input ground, and
• wherein the predetermined bias voltage is less than the output power supply voltage level and the predetermined bias voltage is greater than the input power supply voltage level.

A level shifter comprising:

• a first circuit comprising low-voltage transistors, the first circuit being coupled between a pair of complementary nodes and a first ground, and the first circuit being responsive to an input signal and a complementary input signal generated in a first voltage domain;
• and
• a second circuit comprising high-voltage transistors, the second circuit being coupled between the pair of complementary nodes and an output power supply node in a second voltage domain,
• wherein the second circuit further comprises:
• a cross-coupled pair of transistors coupled between the output power supply node and a second pair of complementary nodes, the cross-coupled pair of transistors having a first doping type;
• a pair of isolation transistors coupled between the second pair of complementary nodes and the pair of complementary nodes, the pair of isolation transistors having a second doping type and being selectively disabled by an isolation control signal;
• and
• a pair of cascode transistors coupled between the second pair of complementary nodes and the first ground, the pair of cascode transistors being configured to receive a predetermined bias voltage,
• wherein the predetermined bias voltage is less than an output power supply voltage on the output power supply node and the predetermined bias voltage is greater than an input power supply voltage level.