Circuit, system and method related to a dual gate transistor arrangement

Abstract

A circuit includes an input node configured to receive a gate control signal for controlling a dual gate transistor arrangement, a first output node configured to be coupled to a first gate node of the dual gate transistor arrangement, a first switch coupled between the input node and the first output node, and a second output node configured to be coupled to a second gate node of the dual gate transistor arrangement and coupled to the input node. A control circuit is configured to, upon detecting that the gate control signal indicates a turn-off of the dual gate transistor arrangement, open the first switch for a first predefined time period, and close the first switch after the first predefined time period.

Dependencies are inferred from the claim text.