Memory device and test method for the memory device

A memory device comprising:

• a memory core including a memory cell array including a plurality of memory cells, the memory cell array being divided into a plurality of memory banks;
• a Built-In Self Test (BIST) circuit configured to select a target memory bank from the plurality of memory banks and perform a parallel test on the target memory bank among the plurality of memory banks;
• and
• a control circuit configured to control the parallel test,
• wherein the BIST circuit includes, for target memory cells included in the target memory bank, a first test circuit configured to determine a defective memory cell and output a first output signal, a second test circuit configured to determine whether the defective memory cell is a single defective memory cell and output a second output signal, and a third test circuit configured to determine whether the defective memory cell is an adjacent double defective memory cell and output a third output signal, and
• wherein the control circuit is configured to
• determine the target memory bank to be a non-defective memory bank when the defective memory cell is the single defective memory cell or the adjacent double defective memory cell.