Memory programming schemes with adjustable verification voltages for reducing data retention loss

An apparatus for data storage, comprising:

• a plurality of memory cells coupled to multiple word lines (WLs), the memory cells configured to store data values in multiple respective predefined programming levels;
• and
• storage circuitry, configured to:
• receive data values for storage in the memory cells of a given WL;
• select memory cells of the given WL that are to store a given data value among the received data values;
• set a verification voltage for programming the selected memory cells, so that a difference between the verification voltage and a read voltage predetermined for the selected memory cells depends on a rate of drift that is expected to occur to a threshold voltage distribution (TVD) associated with the selected memory cells when programmed, by:
• holding a predefined dependency between verification voltages and (i) the given data value, and (ii) one or both of a first neighbor data value previously stored in first neighbor memory cells neighboring the selected memory cells, and a second neighbor data value to be programmed in second neighbor memory cells neighboring the selected memory cells;
• and
• setting the verification voltage using the predefined dependency;
• apply one or more programming pulses to the given WL;
• and
• verify that the selected memory cells have been programmed successfully using the set verification voltage.