Logical block construction for physical blocks comprising multiple erase blocks coupled to a same string

A method, comprising:

• forming, via a controller coupled to a memory array comprising a plurality of physical blocks of memory cells, wherein each physical block of the plurality comprises more than two erase blocks, with each of the more than two erase blocks of each respective physical block comprising memory cells coupled to a same string of memory cells corresponding to the respective physical block, logical block groupings for the erase blocks in accordance with a particular logical block implementation;
• wherein forming the logical block groupings comprises grouping the erase blocks such that each logical block comprises:
• a first erase block adjacent to a first end of a particular string corresponding to a first physical block;
• and
• a second erase block, wherein the second erase block is either:
• located in the first physical block and not adjacent to a second end of the particular string corresponding to the first physical block;
• or
• located in a second physical block and adjacent to a first end of a particular string corresponding to the second physical block;
• and
• performing an operation on the erase blocks based on the formed logical block groupings;
• wherein the method includes determining the logical block groupings such that any erase blocks that are not adjacent to either end of the particular string corresponding to the first physical block or either end of the particular string corresponding to the second physical block are adjacent to an erase block that is adjacent to either end of the particular string corresponding to the first physical block or either end of the particular string corresponding to the second physical block.

An apparatus, comprising:

• a memory array comprising:
• a first physical block of memory cells comprising at least three erase blocks each comprising memory cells coupled to a first string of memory cells corresponding to the first physical block;
• a second physical block of memory cells comprising at least three erase blocks each comprising memory cells coupled to a second string of memory cells corresponding to the second physical block;
• and
• a controller coupled to the memory array and configured to:
• determine a plurality of logical block groupings of the erase blocks of the first and second physical blocks;
• and
• perform a memory operation in accordance with the determined logical block groupings of the erase blocks;
• wherein the plurality of logical block groupings comprises:
• a first grouping comprising a first erase block adjacent to a first end of the first string and a second erase block adjacent to the first erase block;
• a second grouping comprising third erase block adjacent to a first end of the second string and a fourth erase block adjacent to the third erase block;
• and
• a third grouping comprising a fifth erase block adjacent to a second end of the first string and a sixth erase block adjacent to a second end of the second string.

An apparatus, comprising:

• a memory array comprising a plurality of physical blocks of memory cells, wherein each physical block of the plurality comprises more than two erase blocks, with each of the more than two erase blocks of each respective physical block comprising memory cells coupled to a same string of memory cells corresponding to the respective physical block;
• and
• a controller coupled to the memory array and configured to operate the memory array in accordance with a logical block implementation in which each logical block comprises:
• a first erase block adjacent to a first end of a particular string corresponding to a first physical block;
• and
• a second erase block, wherein the second erase block is either:
• located in the first physical block and not adjacent to a second end of the particular string corresponding to the first physical block;
• or
• located in a second physical block and adjacent to a first end of a particular string corresponding to the second physical block;
• wherein the first erase block of a first logical block is adjacent to the first end of the particular string corresponding to the first physical block;
• wherein the second erase block of the first logical block is located in the first physical block and not adjacent to the second end of the particular string corresponding to the first physical block;
• and
• wherein the first erase block of a second logical block is adjacent to a second end of the particular string corresponding to the first physical block.

A method, comprising:

• forming, via a controller coupled to a memory array comprising a plurality of physical blocks of memory cells, wherein each physical block of the plurality comprises more than two erase blocks, with each of the more than two erase blocks of each respective physical block comprising memory cells coupled to a same string of memory cells corresponding to the respective physical block, logical block groupings for the erase blocks in accordance with a particular logical block implementation;
• wherein forming the logical block groupings comprises grouping the erase blocks such that each logical block comprises:
• a first erase block adjacent to a first end of a particular string corresponding to a first physical block;
• and
• a second erase block, wherein the second erase block is either:
• located in the first physical block and not adjacent to a second end of the particular string corresponding to the first physical block;
• or
• located in a second physical block and adjacent to a first end of a particular string corresponding to the second physical block;
• and
• performing an operation on the erase blocks based on the determined logical block groupings;
• and
• wherein at least some of the plurality of physical blocks comprise an even quantity of erase blocks, and wherein the particular logical block implementation comprises grouping the erase blocks such that each logical block comprises half of the erase blocks within a respective one of the at least some of the plurality of physical blocks.