Memory device and erasing and verification method thereof

A method of operating a memory device comprising a memory string, the memory string comprising a top select gate, a memory cell, and a bottom select gate, the top select gate being coupled to a first select line, the memory cell being coupled to a word line, and the bottom select gate being coupled to a second select line;

• the method comprising:
• applying an erasing voltage to the memory string in an erasing stage;
• applying a first voltage to the word line in a first stage of a verification stage, the verification stage being after the erasing stage;
• applying a second voltage to the word line in a second stage of the verification stage, the second stage being after the first stage, and the second voltage being lower than the first voltage;
• applying a third voltage to the word line in the second stage and after applying the second voltage to the word line, wherein the third voltage is larger than the second voltage;
• applying a first turn-on voltage to the second select line before applying the second voltage to the word line;
• and
• applying a second turn-on voltage to the first select line after stopping application of the erasing voltage for a period of time.

A memory system, comprising:

• a memory device comprising:
• a memory string comprising a top select gate, a memory cell, and a bottom select gate, the top select gate being coupled to a first select line, the memory cell being coupled to a word line, and the bottom select gate being coupled to a second select line;
• and
• a control circuit coupled to the first select line, the word line, and the second select line, wherein the control circuit is configured to, in an erasing operation comprising an erasing stage and a verification stage after the erasing stage:
• apply an erasing voltage to the memory string in the erasing stage;
• apply a first voltage to the word line in a first stage of the verification stage;
• apply a second voltage to the word line in a second stage of the verification stage, the second stage being after the first stage, and the second voltage being lower than the first voltage;
• apply a third voltage to the word line in the second stage and after applying the second voltage to the word line, wherein the third voltage is larger than the second voltage;
• apply a first turn-on voltage to the second select line before applying the second voltage to the word line;
• and
• apply a second turn-on voltage to the first select line after stopping application of the erasing voltage for a period of time.