Memory device, integrated circuit device and method

An integrated circuit (IC) device, comprising:

• a substrate;
• an active region continuously extending along a first direction over the substrate;
• a plurality of gate regions extending across the active region along a second direction transverse to the first direction, and dividing the active region into a plurality of source/drain regions, each gate region among the plurality of gate regions arranged between a corresponding pair of source/drain regions among the plurality of source/drain regions, the plurality of source/drain regions comprising:
• first and second source/drain regions, and
• a set of source/drain regions between the first and second source/drain regions;
• in a first metal layer over the plurality of gate regions, a plurality of conductive patterns comprising:
• first and second conductive patterns correspondingly over and electrically coupled to the first and second source/drain regions, and
• a set of conductive patterns between the first and second conductive patterns, and correspondingly over and electrically coupled to the set of source/drain regions;
• and
• a set of data storage elements correspondingly over and electrically coupled to the set of conductive patterns.

A method, comprising:

• forming, over a continuous active region of a substrate, transistors having a set of common source/drain regions between first and second source/drain regions;
• sequentially depositing a first conductive material, a data storage material, and a second conductive material over the set of common source/drain regions, and patterning the deposited first conductive material, data storage material, and second conductive material to obtain a set of data storage elements;
• and
• performing a damascene process, which comprises depositing a dielectric layer over a substrate, patterning the dielectric layer to obtain a damascene structure having via holes and recessed features over the via holes, and filing a conductive material into the via holes and the recessed features of the damascene structure, to correspondingly obtain
• a source line coupling the first and second source/drain regions,
• a first bit line coupling some data storage elements in the set of data storage elements, and
• a second bit line coupling other data storage elements in the set of data storage elements.