Shift register unit, gate drive circuit, display panel, and driving method

A shift register unit, comprising:

• a first shift register configured to output a cascade signal via a cascade output terminal;
• a sampling circuit coupled to a first node and configured to provide a signal from an enable terminal to the first node in response to a signal from a sampling control terminal;
• and
• a control circuit, wherein an input terminal of the control circuit is coupled to the cascade output terminal and the first node;
• and the control circuit is configured to, in response to a signal at the first node, output a gate scan signal with a same timing diagram as the cascade signal via a drive output terminal, or output a gate off signal via the drive output terminal;
• wherein the sampling circuit is further configured to provide the signal from the enable terminal to the first node in response to the signal from the sampling control terminal during a sampling phase;
• wherein the sampling phase is between a start moment of an active level of a cascade signal of a previous-level shift register unit and a start moment of an active level of a cascade signal of a current-level shift register unit;
• wherein the sampling control terminal comprises a first sampling control terminal and a second sampling control terminal;
• wherein the sampling circuit is further configured to provide the signal from the enable terminal to the first node in response to both signals from the first sampling control terminal and the second sampling control terminal;
• wherein a first sampling control terminal of the current-level shift register unit is coupled to a cascade output terminal of the current-level shift register unit, and a second sampling control terminal of the current-level shift register unit is coupled to a cascade output terminal of the previous-level shift register unit;
• wherein the sampling circuit is further configured to provide the signal from the enable terminal to the first node in response to the cascade signal of the current-level shift register unit and the cascade signal of the previous-level shift register unit during the sampling phase;
• or,
• wherein a first sampling control terminal of the current-level shift register unit is coupled to a pull-down node of the current-level shift register unit, and a second sampling control terminal of the current-level shift register unit is coupled to a pull-up node of the current-level shift register unit;
• wherein the sampling circuit is further configured to provide the signal from the enable terminal to the first node in response to a signal at the pull-down node and a signal at the pull-up node of the current-level shift register unit during the sampling phase;
• or,
• wherein the shift register unit further comprises a second shift register;
• wherein the second shift register is coupled to the sampling control terminal and is configured to input a signal to the sampling control terminal based on signals from a sampling control input terminal, a first sampling control clock signal terminal, and a second sampling control clock signal terminal.