Pixel driving circuit and driving method thereof, and display apparatus

A driving method for a pixel driving circuit, wherein the method comprises driving a pixel driving circuit in a scanning cycle, the pixel driving circuit comprises:

• an initializing unit, a data writing unit, a light emitting control unit, a reset unit, a driving transistor and a storage capacitor;
• wherein,
• the initializing unit is configured to transmit an initialization voltage to a second node in response to an initialization scanning signal to charge the storage capacitor;
• the second node is a connection node among a second terminal of the storage capacitor, a control terminal of the driving transistor and a threshold compensation unit;
• the threshold compensation unit is configured to obtain a threshold voltage of the driving transistor in response to a first scanning signal scanned at a first frequency and to update a potential of the second node;
• the data writing unit is configured to transmit a data signal to a first node in response to the first scanning signal or a second scanning signal;
• the first node is a connection node between a first terminal of the driving transistor and the light emitting control unit;
• the reset unit is configured to reset a potential of the first node through a reset voltage in response to the second scanning signal scanned at a second frequency, and to change a forward bias state of an organic light emitting diode at the same time through the initialization voltage;
• and
• the light emitting control unit is configured to transmit a driving current output by the driving transistor to the organic light emitting diode in response to a light emitting control signal to cause the organic light emitting diode to emit light;
• wherein a value of the first frequency ranges from 1 Hz to 30 Hz, a value of the second frequency ranges from 60 Hz to 120 Hz, the second frequency is N times the first frequency, and N takes an integer value in the range of [2, 120],
• wherein the reset unit comprises a first transistor and a seventh transistor, and the data writing unit comprises the first transistor;
• wherein a first terminal of the first transistor is connected to a data line, a second terminal of the first transistor is connected to the first node, and a control terminal of the first transistor is connected to a second scanning line;
• and
• wherein a first terminal of the seventh transistor is connected to an initialization signal terminal, a second terminal of the seventh transistor is connected to an anode of the organic light emitting diode, and a control terminal of the seventh transistor is connected to the second scanning line;
• and wherein the scanning cycle comprises an initialization phase, a data writing phase, a threshold compensation phase, a light emitting phase and a reset phase;
• wherein in the initialization phase:
• a third scanning signal is an operating level signal, and the initializing unit writes an initialization signal into the second node and charges the storage capacitor;
• wherein in the data writing phase and the threshold compensation phase:
• the first scanning signal, or the first scanning signal and the second scanning signal is the operating level signal, the data writing unit writes the data signal into the first node, and the threshold compensation unit writes the threshold compensation voltage at the second node by calling the storage capacitor;
• and
• wherein in the light emitting phase and the reset phase:
• the light emitting control signal is the operating level signal, the light emitting control unit transmits a driving current output by the driving transistor to the organic light emitting diode to control the organic light emitting diode to emit light;
• and the reset unit resets the potential of the first node at the second frequency to control a light emitting device to emit light,
• wherein the reset voltage is provided by the data line during the reset phase,
• wherein the threshold compensation unit comprises a third transistor, wherein a first terminal of the third transistor is connected to the second node, a second terminal of the third transistor is connected to a third node, and a control terminal of the third transistor is connected to a first scanning line,
• wherein the initializing unit comprises a sixth transistor, a first terminal of the sixth transistor is connected to the initialization signal terminal, a second terminal of the sixth transistor is connected to the second node, and a control terminal of the sixth transistor is connected to a third scanning line,
• wherein the pixel driving circuit further comprises a scanning circuit, wherein the scanning circuit comprises a cascaded first gate driver on array circuit, a cascaded second gate driver on array circuit, a cascaded third gate driver on array circuit, and a light emitting control signal driving circuit;
• wherein the third gate driver on array circuit is configured to output a third scanning signal,
• wherein the third scanning signal and the first scanning signal are both output by a same scanning line, the third scanning signal is output by the (n−1)-th stage of the same scanning line, and the first scanning signal is output by the n-th stage of the same scanning line, where n is an integer.

A display apparatus, comprising a pixel driving circuit, wherein the pixel driving circuit comprises:

• an initializing unit, a data writing unit, a light emitting control unit, a reset unit, a driving transistor and a storage capacitor;
• wherein,
• the initializing unit is configured to transmit an initialization voltage to a second node in response to an initialization scanning signal to charge the storage capacitor;
• the second node is a connection node among a second terminal of the storage capacitor, a control terminal of the driving transistor and a threshold compensation unit;
• the threshold compensation unit is configured to obtain a threshold voltage of the driving transistor in response to a first scanning signal scanned at a first frequency and to update a potential of the second node;
• the data writing unit is configured to transmit a data signal to a first node in response to the first scanning signal or a second scanning signal;
• the first node is a connection node between a first terminal of the driving transistor and the light emitting control unit;
• the reset unit is configured to reset a potential of the first node through a reset voltage in response to the second scanning signal scanned at a second frequency, and to change a forward bias state of an organic light emitting diode at the same time through the initialization voltage, wherein the reset voltage is provided by a data line during a reset phase that is not a data writing phase;
• and
• the light emitting control unit is configured to transmit a driving current output by the driving transistor to the organic light emitting diode in response to a light emitting control signal to cause the organic light emitting diode to emit light;
• wherein a value of the first frequency ranges from 1 Hz to 30 Hz, a value of the second frequency ranges from 60 Hz to 120 Hz, the second frequency is N times the first frequency, and N takes an integer value in the range of [2, 120],
• wherein the reset unit comprises a first transistor and a seventh transistor, and the data writing unit comprises the first transistor;
• wherein a first terminal of the first transistor is connected to the data line, a second terminal of the first transistor is connected to the first node, and a control terminal of the first transistor is connected to a second scanning line;
• and
• wherein a first terminal of the seventh transistor is connected to an initialization signal terminal, a second terminal of the seventh transistor is connected to an anode of the organic light emitting diode, and a control terminal of the seventh transistor is connected to the second scanning line,
• wherein the threshold compensation unit comprises a third transistor, wherein a first terminal of the third transistor is connected to the second node, a second terminal of the third transistor is connected to a third node, and a control terminal of the third transistor is connected to a first scanning line,
• wherein the initializing unit comprises a sixth transistor, a first terminal of the sixth transistor is connected to the initialization signal terminal, a second terminal of the sixth transistor is connected to the second node, and a control terminal of the sixth transistor is connected to a third scanning line,
• wherein the pixel driving circuit further comprises a scanning circuit, wherein the scanning circuit comprises a cascaded first gate driver on array circuit, a cascaded second gate driver on array circuit, a cascaded third gate driver on array circuit, and a light emitting control signal driving circuit;
• wherein the third gate driver on array circuit is configured to output a third scanning signal,
• wherein the third scanning signal and the first scanning signal are both output by a same scanning line, the third scanning signal is output by the (n−1)-th stage of the same scanning line, and the first scanning signal is output by the n-th stage of the same scanning line, where n is an integer.