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US 12,762,241 B2Granted
System and method for storing system state data in a hardware register
AssigneeInfineon Technologies Americas Corp.
InventorJacek Dobaczewski
Life of this patent
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Abstract
One or more computing devices, systems, and/or methods are provided. In an example, a method comprises executing an application image to initialize a computing system. System state data associated with the initializing of the computing system is stored in a hardware register having at least one lockable until reset bit. A fault condition is identified responsive to the system state data not matching an expected value.
Claims20
A system, comprising:
- a processor;
- a hardware register comprising at least a first lockable until reset bit and being addressable in a first address range;
- and
- a memory storing an application image comprising instructions, that when executed by the processor cause the processor to:
- store system state data having a first Hamming distance in the first lockable until reset bit of the hardware register during an initializing of the system;
- lock the first lockable until reset bit of the hardware register after storing the system state data in the first lockable until reset bit of the hardware register;
- store a system state verification parameter in the memory at a second address range different than the first address range;
- combine the system state data in the hardware register and the system state verification parameter to generate a combined system state verification parameter having a second Hamming distance greater than the first Hamming distance;
- and
- identify a fault condition responsive to the combined system state verification parameter not matching an expected value after completion of the initialization of the system.
7 more elements
A method, comprising:
- executing an application image to initialize a computing system;
- storing system state data associated with the initializing of the computing system and having a first Hamming distance in a hardware register having at least a first lockable until reset bit and being addressable at a first address range;
- storing a system state verification parameter in a system memory addressable at a second address range different than the first address range;
- combining the system state data and the system state verification parameter to generate a combined system state verification parameter having a second Hamming distance greater than the first Hamming distance;
- and
- identifying a fault condition responsive to the combined system state verification parameter not matching an expected value.
3 more elements
A non-transitory computer-readable medium storing instructions that when executed facilitate performance of operations comprising:
- initializing a computing system comprising a processor;
- storing system state data associated with the initializing of the computing system and having a first Hamming distance in a hardware register comprising at least a first lockable until reset bit and being addressable at a first address range;
- storing a system state verification parameter in a memory addressable at a second address range different than the first address range;
- combining the system state data in the hardware register and the system state verification parameter to generate a combined system state verification parameter having a second Hamming distance greater than the first Hamming distance;
- and
- identifying a fault condition responsive to the combined system state verification parameter not matching an expected value after completion of the initialization of the computing system.
3 more elements
Dependencies are inferred from the claim text.