System for implementing operations having dynamically-sized data structures on a reconfigurable processor

A method of operating a data processing system that comprises a reconfigurable processor, comprising:

• configuring the reconfigurable processor such that the reconfigurable processor implements:
• a first operation that generates an output, wherein a size of the output is unknown during a configuration phase,
• a second operation that receives the output of the first operation as an input,
• a write operation that stores the output in a buffer, wherein the first operation is enabled to write a first portion of the output to a first portion of the buffer, while the second operation reads a first portion of the input that is different than the first portion of the output from a second portion of the buffer that is different than the first portion of the buffer, and
• control circuitry that comprises:
• a control unit circuitry that directs the second operation during a read operation following the write operation to read data as the input from the buffer that was stored during the write operation.

A non-transitory computer-readable storage medium including instructions that, when executed by a processing unit, cause the processing unit to operate a data processing system that comprises a reconfigurable processor, the instructions comprising:

• configuring the reconfigurable processor with configuration data such that the reconfigurable processor implements:
• a first operation that generates an output, wherein a size of the output is unknown,
• a second operation that receives the output of the first operation as an input,
• a write operation that stores the output in a buffer, wherein the first operation is enabled to write a first portion of the output to a first portion of the buffer, while the second operation reads a first portion of the input that is different than the first portion of the output from a second portion of the buffer that is different than the first portion of the buffer, and
• control circuitry that comprises a control unit circuitry that directs the second operation during a read operation following the write operation to read data as the input from the buffer that was stored during the write operation.