Logical-to-physical mapping for zoned namespace memory systems with a data cache

A method, comprising:

• receiving, by a memory system, a write command comprising data and a set of logical block addresses associated with the data, the data for storage in a memory array of the memory system, wherein the set of logical block addresses is associated with one or more zones of memory cells of a plurality of zones of memory cells in the memory array;
• storing, to a cache of the memory system based at least in part on the write command, one or more entries that map the set of logical block addresses to respective physical addresses of a plurality of physical addresses in the cache, wherein each entry of the one or more entries comprises mapping information for a respective zone of the one or more zones of memory cells;
• writing the data to the respective physical addresses in the cache based at least in part on storing the one or more entries in the cache;
• and
• transferring the data from the cache to the one or more zones in the memory array based at least in part on writing the data to the respective physical addresses in the cache.

A non-transitory computer-readable medium storing code, the code comprising instructions executable by one or more processors to:

• receive, by a memory system, a write command comprising data and a set of logical block addresses associated with the data, the data for storage in a memory array of the memory system, wherein the set of logical block addresses is associated with one or more zones of memory cells of a plurality of zones of memory cells in the memory array;
• store, to a cache of the memory system based at least in part on the write command, one or more entries that map the set of logical block addresses to respective physical addresses of a plurality of physical addresses in the cache, wherein each entry of the one or more entries comprises mapping information for a respective zone of the one or more zones of memory cells;
• write the data to the respective physical addresses in the cache based at least in part on storing the one or more entries in the cache;
• and
• transfer the data from the cache to the one or more zones in the memory array based at least in part on writing the data to the respective physical addresses in the cache.

A memory system, comprising:

• one or more caches comprising a plurality of single-level memory cells;
• one or more memory arrays coupled with the one or more caches and comprising a plurality of multi-level memory cells, wherein the plurality of multi-level memory cells are included in a plurality of zones, each zone comprising one or more blocks of memory cells;
• and
• processing circuitry configured to:
• receive a write command comprising data and a set of logical block addresses associated with the data, the data for storage in the one or more memory arrays, wherein the set of logical block addresses is associated with one or more zones of the plurality of zones of the one or more memory arrays;
• store, to a logical-to-physical (L2P) table in a cache of the one or more caches based at least in part on the write command, one or more L2P entries that map the set of logical block addresses to respective physical addresses of a plurality of physical addresses in the cache, wherein each L2P entry of the one or more L2P entries comprises mapping information for a respective zone of the one or more zones, and wherein a size of each zone of the one or more zones corresponds to an integer quantity of L2P entries of the one or more L2P entries;
• write the data to the respective physical addresses in the cache based at least in part on storing the one or more L2P entries in the L2P table, wherein the cache is configured to store data for a subset of the plurality of zones that comprises the one or more zones;
• copy the data from the cache to the one or more zones in the one or more memory arrays based at least in part on writing the data to the respective physical addresses in the cache;
• and
• deallocate, based at least in part on copying the data from the cache to the one or more zones in the one or more memory arrays, one or more portions of the cache allocated for storing one or more groups of L2P entries.

A method, comprising:

• receiving, by a memory system, a write command comprising data and a set of logical block addresses associated with the data, the data for storage in a memory array of the memory system, wherein the set of logical block addresses is associated with one or more zones of multi-level memory cells of a plurality of zones of multi-level memory cells in the memory array;
• storing, to a logical-to-physical (L2P) table in one or more single-level memory cells of a cache of the memory system based at least in part on the write command, one or more L2P entries that map the set of logical block addresses to respective physical addresses of a plurality of physical addresses in the cache, wherein each L2P entry of the one or more L2P entries comprises mapping information for a respective zone of the one or more zones of multi-level memory cells, and wherein a size of each zone of the one or more zones corresponds to an integer quantity of L2P entries of the one or more L2P entries;
• writing the data to the respective physical addresses in the cache based at least in part on storing the one or more L2P entries in the L2P table, wherein the cache is configured to store data for a subset of the plurality of zones that comprises the one or more zones;
• transferring the data from the one or more single-level memory cells of the cache to the one or more zones of multi-level memory cells in the memory array based at least in part on writing the data to the respective physical addresses in the cache;
• and
• deallocating, based at least in part on transferring the data from the cache to the one or more zones in the memory array, one or more portions of the cache allocated for storing one or more groups of L2P entries.