Semiconductor memory apparatus configured to perform an error check
AssigneeSK hynix Inc.
InventorJi Soo Kim
Life of this patent
Estimating the term…
Abstract
A semiconductor memory apparatus includes an encoding circuit, a read path circuit, a transmitter circuit, and a read error check circuit. The encoding circuit is configured to encode bank data to generate a read symbol. The read path circuit is configured to transmit the read symbol to the transmitter circuit. The transmitter circuit is configured to generate a multi-level signal based on the read symbol. The read error check circuit is configured to determine whether an error has occurred in the transmission of the read symbol from the encoding circuit to the transmitter circuit through the read path circuit.
Claims17
A semiconductor memory apparatus comprising:
- an encoding circuit configured to encode bank data output from a memory cell array to generate a read symbol and configured to generate a first check bit from the read symbol;
- a read path circuit configured to transmit the read symbol;
- a transmitter circuit configured to generate a multi-level signal based on the read symbol received from the read path circuit, and configured to generate a second check bit from the read symbol;
- and
- a read error check circuit configured to generate a read error signal based on the first check bit and the second check bit.
A semiconductor memory apparatus comprising:
- a first memory bank that outputs a first bank data;
- a second memory bank that outputs a second bank data;
- a first encoding circuit configured to encode the first bank data to generate a first read symbol, and configured to generate a first check bit from the first read symbol;
- a second encoding circuit configured to encode the second bank data to generate a second read symbol, and configured to generate a second check bit from the second read symbol;
- a first read path circuit configured to transmit the first read symbol, and configured to output one of the first read symbol and the second read symbol as a first selected read symbol based on a channel selection signal;
- a second read path circuit configured to transmit the second read symbol, and configured to provide the second read symbol to the first read path circuit or output the second read symbol as a second selected read symbol based on a channel mode signal;
- a first transmitter circuit configured to generate a first multi-level signal based on the first selected read symbol, and configured to generate a third check bit from the first selected read symbol;
- a second transmitter circuit configured to generate a second multi-level signal based on the second selected read symbol, and configured to generate a fourth check bit from the second selected read symbol;
- a first read error check circuit configured to generate a first read error signal based on one of the first and second check bits and the third check bit based on the channel selection signal;
- and
- a second read error check circuit configured to generate a second read error signal based on the second and fourth check bits.
Dependencies are inferred from the claim text.