Streaming engine with deferred exception reporting

A device comprising:

• a cache memory controller that includes:
• an interface configured to couple to a cache memory;
• a head register coupled to the interface and configured to couple to a processor core;
• and
• a set of fault registers;
• wherein the cache memory controller is configured to, based on an instruction that specifies a data stream:
• provide, via the interface, a set of memory accesses to retrieve at least a portion of the data stream from the cache memory;
• receive, via the interface, the at least a portion of the data stream from the cache memory;
• determine whether a fault occurred associated with a first data element of the data stream;
• based on the fault, store an identifier of the fault in the set of fault registers;
• receive a request from the processor core to provide the first data element from the head register;
• defer reporting of the fault to the processor core until the request is received;
• and
• in a debug mode, provide the identifier of the fault from the set of fault registers.

A method comprising:

• receiving a stream open instruction that specifies a set of data;
• and
• based on the stream open instruction, performing by a cache controller:
• requesting a first data element of the set of data;
• detecting a fault associated with the first data element;
• storing an identifier of the fault in a set of fault registers;
• delaying reporting of the fault to a processor core until a request is received from the processor core for the first data element;
• entering into a debug mode;
• and
• in the debug mode, providing the identifier of the fault.