Flash memory controller and flash memory access method

A method for improving access efficiency of a flash memory, for use in a flash memory controller coupled to the flash memory, the method comprising:

• receiving, by a decoder, channel values read from the flash memory;
• and
• performing, by the decoder, a decoding process on the channel values in an iterative manner according to a parity check matrix of a quasi-cyclic low-density parity-check (QC-LDPC) code, wherein the decoding process involves a plurality of Q messages and a plurality of R messages, and the decoding process comprises the following steps:
• calculating, using a shift parameter unit comprising a memory storing a base matrix and a pipeline register for storing a shift parameter matrix, a first shift parameter and a second shift parameter based on the shift parameter matrix, wherein the first shift parameter is a difference between a specific first column and a specific second column of the shift parameter matrix, the specific first column being adjacent to the specific second column, and the second shift parameter is a difference between a specific third column and a specific fourth column of the shift parameter matrix, the specific third column being adjacent to the specific fourth column;
• updating, using a variable node block, the plurality of Q messages based on the channel values and the plurality of R messages;
• performing circular shift, using a first shift block, on the plurality of Q messages to generate a plurality of Q′ messages according to the first shift parameter;
• circularly shifting, using a second shift block, a plurality of status data S according to the second shift parameter to generate a plurality of status data S′, wherein each of the plurality of status data S comprises a minimum value, a second minimum value, an index of the minimum value, and a global sign value;
• and
• updating, using a check node block, the plurality of R messages based on the plurality of Q′ messages and the plurality of status data S′ and outputting the plurality of status data S;
• wherein the shift parameter unit outputs each column of the base matrix sequentially to the pipeline register for each clock cycle.

A method for improving access efficiency of a flash memory, for use in a flash memory controller coupled to the flash memory, the method comprising:

• receiving, by a decoder, channel values read from the flash memory;
• and
• performing, by the decoder, a decoding process of a quasi-cyclic low-density parity-check (QC-LDPC) code, wherein the decoding process involves a plurality of Q messages and a plurality of R messages, and the decoding process comprises the following steps:
• generating, using a shift parameter unit, a first shift parameter and a second shift parameter based on a X×Y base matrix of the QC-LDPC code;
• updating, using a variable node block, the plurality of Q messages based on the channel values read from the flash memory and the plurality of R messages;
• generating, using a first shift block, a plurality of Q′ messages based on the plurality of Q messages and the first shift parameter;
• generating, using a second shift block, a plurality of status data S′ by performing circular shift on a plurality of status data S according to the second shift parameter;
• and
• updating, using a check node block, the plurality of R messages and outputting the plurality of status data S based on the plurality of Q′ messages and the plurality of status data S′, wherein each status data S comprises a minimum value, a second minimum value, an index of the minimum value, and a global sign value.