Runtime storage capacity reduction avoidance in sequentially-written memory devices

A method comprising:

• accessing, by a processing device, a memory device comprising a plurality of blocks, wherein each block of a first subset of the plurality of blocks is configured to store a first number of bits and each block of a second subset of the plurality of blocks is configured to store a second number of bits, wherein the second number of bits is greater than the first number of bits;
• determining that a first block of a set of blocks of the first subset is a bad block;
• identifying a second block of the set of blocks that is paired with the first block in association with a zone of a logical block address space of the memory device;
• and
• causing, by the processing device, an erase operation to be performed on the second block of the set of blocks to configure the second block to store the second number of bits.

A non-transitory computer-readable storage medium storing instructions, which when executed by a processing device, cause the processing device to perform operations comprising:

• accessing a memory device comprising a plurality of blocks, wherein each block of a first subset of the plurality of blocks is configured to store a first number of bits and each block of a second subset of the plurality of blocks is configured to store a second number of bits, wherein the second number of bits is greater than the first number of bits;
• determining that a first block of a set of blocks of the first subset is a bad block;
• identifying a second block of the set of blocks that is paired with the first block in association with a zone of a logical block address space of the memory device;
• and
• causing an erase operation to be performed on the second block of the set of blocks to configure the second block to store the second number of bits.