Erasable programmable non-volatile memory cell

An erasable programmable non-volatile memory cell, comprising:

• an isolation structure formed on a P-type semiconductor substrate, wherein a surface of the P-type semiconductor substrate is divided into a first region and a second region by the isolation structure;
• a first P-well region formed in the P-type semiconductor substrate and corresponding to the first region;
• a second P-well region formed in the P-type semiconductor substrate and corresponding to the second region, wherein the first P-well region and the second P-well region are in contact with each other;
• an N-type isolation region, wherein the N-type isolation region is arranged between the first P-well region and the P-type semiconductor substrate to isolate the first P-well region from the P-type semiconductor substrate, the N-type isolation region is arranged between the second P-well region and the P-type semiconductor substrate to isolate the second P-well region from the P-type semiconductor substrate;
• a first gate structure and a second gate structure formed on the first region, wherein the first region is divided into a first merged doped region, a second merged doped region and a third merged doped region by the first gate structure and the second gate structure;
• and
• a fourth merged doped region formed in the P-type semiconductor substrate and corresponding to the second region, and located beside the second gate structure,
• wherein the second gate structure is externally extended to the second region through a surface of the isolation structure, and a portion of the second region is covered by the second gate structure,
• wherein the first merged doped region, the first gate structure and the second merged doped region are collaboratively formed as a select transistor, the second merged doped region, the second gate structure and the third merged doped region are collaboratively formed as a floating gate transistor, and the second gate structure and the fourth merged doped region are collaboratively formed as a MOS capacitor, wherein when a program action is performed, the a voltage of the first P-well region is lower than a voltage of the first merged doped region and a voltage of the third merged doped region.