Semiconductor package having lead frame with slanted sections

A semiconductor package comprising:

• a lead frame comprising
• a top plate comprising:
• a thicker region;
• and
• a thinner region;
• a plurality of drain pads;
• a plurality of slanted sections, each slanted section of the plurality of slanted sections connecting a respective drain pad of the plurality of drain pads to the top plate;
• a gate pad;
• and
• a plurality of source pads;
• a chip attached to the lead frame, the chip comprising:
• a source electrode and a gate electrode on a top surface of the chip;
• and
• a drain electrode on a bottom surface of the chip;
• a molding encapsulation enclosing the chip and a majority portion of the lead frame, the molding encapsulation comprises:
• a top surface;
• a first side surface;
• a second side surface opposite the first side surface;
• and
• a bottom surface;
• wherein a respective side surface of each drain pad of the plurality of drain pads is exposed from the first side surface of the molding encapsulation;
• wherein a respective bottom surface of each drain pad of the plurality of drain pads is exposed from the bottom surface of the molding encapsulation;
• wherein a top surface of the thicker region of the top plate of the lead frame is exposed from the top surface of the molding encapsulation;
• wherein a side surface of the gate pad is exposed from the second side surface of the molding encapsulation;
• wherein a bottom surface of the gate pad is exposed from the bottom surface of the molding encapsulation;
• wherein a respective side surface of each source pad of the plurality of source pads is exposed from the second side surface of the molding encapsulation;
• and
• wherein a respective bottom surface of each source pad of the plurality of source pads is exposed from the bottom surface of the molding encapsulation.