Complementary field effect transistor (CFET) circuits with vertical routing structures

A method of fabricating a semiconductor structure, the method comprising:

• providing at least one complementary field effect transistor (CFET) structure, comprising:
• providing a first field effect transistor (FET) of a first charge carrier type, comprising a first S/D region, a second S/D region, and a first gate;
• providing a second FET of a second charge carrier type, disposed above the first FET in a Z direction and comprising a third S/D region, a fourth S/D region, and a second gate;
• providing a frontside (FS) metal (FM) layer disposed above the second FET in the Z direction and comprising an FM conductor extending in an X direction;
• providing a vertical connector extending in the Z direction and being electrically coupled to the FM conductor;
• and
• providing a backside (BS) metal (BM) layer disposed below the first FET in the Z direction and comprising a BM conductor extending in the X direction and being electrically coupled to the vertical connector,
• providing additional FM conductors to create a plurality of FM conductors extending in the X direction and spaced apart from each other along a Y direction;
• providing additional BM conductors to create a plurality of BM conductors extending in the X direction and spaced apart from each other along the Y direction;
• and
• providing a second vertical connector that electrically couples the second S/D region to the fourth S/D region by direct contact with both the second S/D region and the fourth S/D region.