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US 12,757,471 B2Granted
Gate structure in high-κ metal gate technology
AssigneeTaiwan Semiconcutor Manufacturing Company, Ltd.
InventorsWei Cheng Wu, Alexander Kalnitsky, Shih-Hao Lo, Hung-Pin Ko
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Abstract
Various embodiments of the present disclosure are directed towards an integrated chip including a gate dielectric structure on a semiconductor substrate. A gate electrode structure is on the gate dielectric structure. The gate electrode structure includes a lower conductive structure and a gate body structure. The gate body structure includes an upper segment over a top surface of the lower conductive structure and a lower segment disposed between opposing inner sidewalls of the lower conductive structure.
Claims20
An integrated chip, comprising:
- a gate dielectric structure on a semiconductor substrate;
- and
- a gate electrode structure on the gate dielectric structure, wherein the gate electrode structure comprises a lower conductive structure and a gate body structure, wherein the gate body structure comprises an upper segment over a top surface of the lower conductive structure and a lower segment disposed between opposing inner sidewalls of the lower conductive structure, wherein the lower segment is T-shaped and the upper segment overlies the lower segment, wherein the upper segment comprises a first conductive material and the lower segment comprises a second conductive material different from the first conductive material, wherein the lower conductive structure comprises a plurality of conductive layers including a first conductive layer and a second conductive layer, wherein the first conductive layer comprises a material different from a material of the second conductive layer.
An integrated chip, comprising:
- a gate dielectric structure on a semiconductor substrate;
- a pair of source/drain regions in the semiconductor substrate and on opposing sides of the gate dielectric structure;
- and
- a gate electrode structure on the gate dielectric structure, wherein the gate electrode structure comprises a lower conductive structure on the gate dielectric structure, a conductive gate layer on the lower conductive structure, and a silicide layer on the conductive gate layer, wherein opposing sidewalls of the silicide layer are aligned with opposing sidewalls of the lower conductive structure, wherein inner sidewalls of the lower conductive structure contact first opposing sidewalls of the conductive gate layer, wherein a bottom surface of the silicide layer is vertically offset from a top surface of the lower conductive structure by a lateral segment of the conductive gate layer, wherein a height of the lateral segment is less than a height of the silicide layer, wherein the height of the silicide layer is less than a height of the lower conductive structure.
1 more element
An integrated chip, comprising:
- a gate dielectric structure over a semiconductor substrate;
- a pair of source/drain regions on opposing sides of the gate dielectric structure;
- a gate electrode over the gate dielectric structure, wherein the gate electrode comprises a conductive structure, a first gate layer, and a second gate layer, wherein the conductive structure comprises a first conductive layer and a second conductive layer, wherein top surfaces of the first and second conductive layers define a top surface of the conductive structure, wherein the first conductive layer comprises a first material and the second conductive layer comprises a second material different from the first material, wherein the first gate layer extends along the top surface of the conductive structure and contacts inner sidewalls of the conductive structure, wherein the second gate layer overlies the first gate layer;
- a dielectric structure on the semiconductor substrate, wherein the dielectric structure laterally surrounds the gate dielectric structure and the gate electrode, wherein a top surface of the dielectric structure is aligned with a top surface of the second gate layer, and wherein a distance between the top surface of the dielectric structure and the top surface of the conductive structure is greater than a height of the second gate layer;
- and
- a conductive via arranged on the second gate layer.
3 more elements
Dependencies are inferred from the claim text.