Semiconductor device and method of fabricating the same

A semiconductor device, comprising:

• a first channel separation structure extending in a first direction;
• a second channel separation structure spaced apart from the first channel separation structure in a second direction intersecting the first direction and extending in the first direction;
• a plurality of first gate structures spaced apart from each other in the first direction between the first and second channel separation structures, the plurality of first gate structures being in contact with the first and second channel separation structures and including respective first gate electrodes and respective first gate insulating films;
• gate capping patterns on the respective first gate electrodes and in contact with the first and second channel separation structures;
• gate spacers on sidewalls of the plurality of first gate structures, respectively;
• first channel patterns including a respective plurality of first sheet patterns, which are spaced apart from each other in a third direction, perpendicular to the first and second directions, and are in contact with the first channel separation structure;
• second channel patterns including a respective plurality of second sheet patterns, which are spaced apart from each other in the third direction and are in contact with the second channel separation structure;
• first source/drain patterns between the first and second channel separation structures and respectively in contact with the first channel patterns;
• second source/drain patterns between the first and second channel separation structures and respectively in contact with the second channel patterns;
• and
• first gate separation structures between the first source/drain patterns and the second source/drain patterns,
• wherein
• an upper surface of the first channel separation structure is coplanar with upper surfaces of the first gate separation structures, and
• an upper surface of the first channel separation structure is coplanar with upper surfaces of the gate capping patterns.

A semiconductor device, comprising:

• a first lower pattern extending in a first direction;
• a second lower pattern extending in the first direction and spaced apart from the first lower pattern in a second direction intersecting the first direction;
• a field insulating film between the first and second lower patterns;
• a first channel separation structure on the first lower pattern and extending in the first direction, a part of the first channel separation structure being in the first lower pattern;
• a second channel separation structure on the second lower pattern and extending in the first direction, a part of the second channel separation structure being in the second lower pattern;
• a plurality of gate structures spaced apart from each other in the first direction between the first and second channel separation structures and in contact with the first and second channel separation structures, the plurality of gate structures including respective gate electrodes and respective gate insulating films;
• first channel patterns between the first channel separation structure and the plurality of gate structures and including a respective plurality of first sheet patterns, which are spaced apart from each other in a third direction, perpendicular to the first and second directions, and are in contact with the first channel separation structure;
• second channel patterns between the second channel separation structure and the plurality of gate structures and including a respective plurality of second sheet patterns, which are spaced apart from each other in the third direction and are in contact with the second channel separation structure;
• first source/drain patterns between the first and second channel separation structures and respectively in contact with the first channel patterns;
• second source/drain patterns between the first and second channel separation structures and respectively in contact with the second channel patterns;
• and
• gate separation structures between the first source/drain patterns and the second source/drain patterns that face the first source/drain patterns in the second direction, the gate separation structures being in contact with the field insulating film.