Trench-gate semiconductor device with trench including buried source

A trench-gate semiconductor device, the semiconductor device comprising one or more unit cells arranged in a semiconductor region, wherein each unit cell comprises:

• the semiconductor region formed by a semiconductor substrate of a first charge type;
• an epitaxial layer of the first charge type arranged on top of the semiconductor substrate;
• a body region of a second charge type different from the first charge type;
• a first trench;
• a second trench extending from a bottom of the first trench, wherein the second trench is narrower than the first trench;
• a first oxide layer arranged on a first side wall of the first trench and forming a gate oxide of a unit cell of the one or more unit cells;
• a second oxide layer arranged on a second side wall and a bottom of the second trench so that the second trench including the second oxide layer is narrower than the first trench including the first oxide layer;
• a first polysilicon region arranged inside the first trench, separated from the first side wall by the first oxide layer, and forming a gate of the unit cell, wherein the body region is separated from the first polysilicon region by the first oxide layer;
• a second polysilicon region arranged inside the second trench, separated from the second side wall and the bottom of the second trench by the second oxide layer, and forming a buried source of the unit cell;
• and
• a third oxide layer arranged in between the first polysilicon region and the second polysilicon region to form a contiguous oxide region, wherein the body region has a bottom surface that is spaced higher than an entire top surface of the contiguous oxide region where the third oxide layer joins with the first oxide layer arranged vertically on the first side wall.